 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? 2000 microchip technology inc. advanced information ds30475a-page 1 high performance risc cpu: ? c-compiler optimized architecture instruction set linear program memory addressing to 32 kbytes linear data memory addressing to 4 kbytes up to 10 mips operation: - dc - 40 mhz clock input - 4 mhz - 10 mhz osc./clock input with pll active 16-bit wide instructions, 8-bit wide data path priority levels for interrupts 8 x 8 single cycle hardware multiplier peripheral features: high current sink/source 25 ma/25 ma up to 76 i/o with individual direction control four external interrupt pins timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler timer1 module: 16-bit timer/counter timer2 module: 8-bit timer/counter with 8-bit period register (time base for pwm) timer3 module: 16-bit timer/counter secondary oscillator clock option - timer1/timer3 two capture/compare/pwm (ccp) modules ccp pins can be configured as: - capture input: 16-bit, max resolution 6.25 ns - compare is 16-bit, max resolution 100 ns (t cy ) - pwm output: pwm resolution is 1- to 10-bit. max. pwm freq. @:8-bit resolution = 156 khz 10-bit resolution = 39 khz master synchronous serial port (mssp) with two modes of operation: - 3-wire spi? (supports all 4 spi modes) -i 2 c? master and slave mode addressable usart module: supports interrupt on address bit advanced analog features: 10-bit analog-to-digital converter module (a/d) with: - fast sampling rate - conversion available during sleep - dnl = 1 lsb, inl = 1 lsb - up to 16 channels available analog comparator module: - 2 comparators - programmable input and output multiplexing comparator voltage reference module programmable low voltage detection (lvd) module - supports interrupt on low voltage detection programmable brown-out reset (bor) can bus module features: message bit rates up to 1 mbps conforms to can 2.0b active spec with: - 29-bit identifier fields - 8 byte message length 3 transmit message buffers with prioritization 2 receive message buffers 6 full 29-bit acceptance filters prioritization of acceptance filters multiple receive buffers for high priority messages to prevent loss due to overflow advanced error management features special microcontroller features: power-on reset (por), power-up timer (pwrt), and oscillator start-up timer (ost) watchdog timer (wdt) with its own on-chip rc oscillator programmable code protection power saving sleep mode selectable oscillator options, including: - 4x phase lock loop (of primary oscillator) - secondary oscillator (32 khz) clock input in-circuit serial programming (icsp?) via two pins cmos technology: low power, high speed eprom technology fully static design wide operating voltage range (2.5v to 5.5v) industrial and extended temperature ranges low power consumption device program memory on-chip ram (bytes) on-chip off-chip eprom (bytes) # single word instructions maximum addressing (bytes) pic18c658 32 k 16384 n/a 1536 pic18c858 32 k 16384 n/a 1536 pic18cxx8 high-performance microcontrollers with can module
pic18cxx8 ds30475a-page 2 advanced information ? 2000 microchip technology inc. pin diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 re2/cs re3 re4 re5 re6 re7/ccp2 rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 re1/wr re0/rd rg0/cantx1 rg1/cantx2 rg2/canrx rg3 mclr /v pp rg4 v ss v dd rf7 rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4 rb5 rb6 v ss osc2/clko/ra6 osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo 64-pin tqfp pic18c658 ? 2000 microchip technology inc. advanced information ds30475a-page 3 pic18cxx8 pin diagrams (cont.?d) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 6867666564636261 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4 rb5 rb6 v ss nc osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 re1/wr re0/rd rg0/cantx1 rg1/cantx2 rg2/canrx rg3 mclr /v pp rg4 v ss v dd rf7 rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out re2/cs re3 re4 re5 re6 re7/ccp2 rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 rf1/an6/c2out rf0/an5 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo osc2/clko/ra6 nc nc nc v ss 68-pin plcc pic18c658 pic18cxx8 ds30475a-page 4 advanced information ? 2000 microchip technology inc. pin diagrams ( cont. ? d) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/cs re3 re4 re5 re6 re7/ccp2 rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 re1/wr re0/rd rg0/cantx1 rg1/cantx2 rg2/canrx rg3 mclr /v pp rg4 v ss v dd rf7 rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4 rb5 rb6 v ss osc2/clko/ra6 osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo rj0 rj1 rh1 rh0 1 2 rh2 rh3 17 18 rh7/an15 rh6/an14 rh5/an13 rh4/an12 rk1 rk0 37 rk3 rk2 50 49 rj2 rj3 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 80-pin tqfp pic18c858 ? 2000 microchip technology inc. advanced information ds30475a-page 5 pic18cxx8 pin diagrams (cont. ? d) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9876 54321 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4 rb5 rb6 v ss nc osc1/clki v dd rb7 rc4/sdi/sda rc3/sck/scl rc2/ccp1 re1/wr re0/rd rg0/cantx1 rg1/cantx2 rg2/canrx rg3 mclr /v pp rg4 v ss v dd rf7 rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out re2/cs re3 re4 re5 re6 re7/ccp2 rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 rf1/an6/c2out rf0/an5 av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/ss /an4/lvdin rc1/t1osi rc0/t1oso/t13cki rc7/rx/dt rc6/tx/ck rc5/sdo rj2 rj3 rj0 rj1 rk0 rk1 rk3 rk2 rh1 rh0 rh2 rh3 rh5/an13 rh4/an12 rh7/an15 rh6/an14 67 66 65 64 63 62 61 68 74 73 72 71 70 76 79 78 77 80 83 82 81 84 75 69 osc2/clko/ra6 nc nc nc 84-pin plcc pic18c858 pic18cxx8 ds30475a-page 6 advanced information ? 2000 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 oscillator configurations ................................................................................................... ......................................................... 21 3.0 reset ....................................................................................................................... ................................................................... 29 4.0 memory organization ......................................................................................................... ........................................................ 41 5.0 table reads/table writes .................................................................................................... ...................................................... 65 6.0 8 x 8 hardware multiplier ................................................................................................... ........................................................ 71 7.0 interrupts .................................................................................................................. .................................................................. 75 8.0 i/o ports ................................................................................................................... .................................................................. 89 9.0 parallel slave port ......................................................................................................... ........................................................... 109 10.0 timer0 module .............................................................................................................. ........................................................... 113 11.0 timer1 module .............................................................................................................. ........................................................... 117 12.0 timer2 module .............................................................................................................. ........................................................... 121 13.0 timer3 module .............................................................................................................. ........................................................... 123 14.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 127 15.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 135 16.0 addressable universal synchronous asynchronous receiver transmitter (usart)................................................ .............. 167 17.0 can module ................................................................................................................. ............................................................ 183 18.0 10-bit analog-to-digital converter (a/d) module ............................................................................ .......................................... 227 19.0 comparator module.......................................................................................................... ........................................................ 237 20.0 comparator voltage reference module ........................................................................................ ........................................... 243 21.0 low voltage detect ......................................................................................................... ......................................................... 247 22.0 special features of the cpu ................................................................................................ .................................................... 251 23.0 instruction set summary .................................................................................................... ...................................................... 261 24.0 development support........................................................................................................ ....................................................... 305 25.0 electrical characteristics ................................................................................................. ......................................................... 311 26.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 341 27.0 packaging information...................................................................................................... ........................................................ 343 appendix a: data sheet revision history ......................................................................................... ............................................. 349 appendix b: device differences.................................................................................................. ................................................... 349 appendix c: device migrations ................................................................................................... ................................................... 350 appendix d: migrating from other picmicro devices ............................................................................... ...................................... 350 appendix e: development tool version requirements ............................................................................... .................................. 351 index .......................................................................................................................... ........................................................................ 353 on-line support................................................................................................................ ................................................................. 361 reader response ................................................................................................................ .............................................................. 362 pic18cxx8 product identification system ........................................................................................ ................................................ 363 ? 2000 microchip technology inc. advanced information ds30475a-page 7 pic18cxx8 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro - chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be re fined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792- 4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the version number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchip ? s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literature center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de lit- erature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products. pic18cxx8 ds30475a-page 8 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 9 pic18cxx8 1.0 device overview this document contains device specific information for the following three devices: 1. pic18c658 2. pic18c858 the pic18c658 is available in 64-pin tqfp and 68-pin plcc packages. the pic18c858 is available in 80-pin tqfp and 84-pin plcc packages. an overview of features is shown in table 1-1. the following two figures are device block diagrams sorted by pin count; 64/68-pin for figure 1-1 and 80/84-pin for figure 1-2. the 64/68-pin and 80/84-pin pinouts are listed in table 1-2. table 1-1: device features features pic18c658 pic18c858 operating frequency dc - 40 mhz dc - 40 mhz program memory internal bytes 32 k 32 k # of single word instructions 16384 16384 data memory (bytes) 1536 1536 interrupt sources 21 21 i/o ports ports a ? g ports a ? h, j, k timers 4 4 capture/compare/pwm modules 2 2 serial communications mssp, can addressable usart mssp, can addressable usart parallel communications psp psp 10-bit analog-to-digital module 12 input channels 16 input channels analog comparators 2 2 resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) por, bor, reset instruction, stack full, stack underflow (pwrt, ost) programmable low voltage detect yes yes programmable brown-out reset yes yes can module yes yes in-circuit serial programming (icsp ? )yes yes instruction set 75 instructions 75 instructions packages 64-pin tqfp 68-pin cerquad (windowed) 68-pin plcc 80-pin tqfp 84-pin cerquad (windowed) 84-pin plcc pic18cxx8 ds30475a-page 10 advanced information ? 2000 microchip technology inc. figure 1-1: pic18c658 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rb7:rb4 rc0/t1oso/t13cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt brown-out reset usart comparator synchronous bor timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 can module timing generation 10-bit adc rb1/int1 data latch data ram ( 1.5 k ) address latch address<12> 12 bank0, f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bitop 8 8 alu<8> 8 address latch program memory (32 kbytes) data latch 20 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> tablelatch 8 ir 12 3 romlatch timer3 portd rd7/psp7:rd0/psp0 ccp2 rb2/int2 rb3/int3 pclatu pcu precision reference bandgap porte portf rf6/an11:rf0/an5 portg rg0/cantx1 rg1/cantx2 rg2/canrx rg3 rg4 timer0 ccp1 rf7 re6 re7/ccp2 re5 re4 re3 re2/cs re0/rd re1/wr lvd ra6 ? 2000 microchip technology inc. advanced information ds30475a-page 11 pic18cxx8 figure 1-2: pic18c858 block diagram power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control osc1/clki osc2/clko mclr v dd , v ss porta portb portc ra4/t0cki ra5/an4/ss /lvdin rb0/int0 rb7:rb4 rc0/t1oso/t13cki rc1/t1osi rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt brown-out reset usart comparator synchronous bor timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 can module timing generation 10-bit adc rb1/int1 data latch data ram ( 1.5 k ) address latch address<12> 12 bank0, f bsr fsr0 fsr1 fsr2 inc/dec logic decode 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bitop 8 8 alu<8> 8 address latch program memory (32 kbytes) data latch 20 21 16 8 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> tablelatch 8 ir 12 3 romlatch timer3 portd rd7/psp7:rd0/psp0 ccp2 rb2/int2 rb3/int3 pclatu pcu precision reference bandgap porte portf rf6/an11:rf0/an5 portg rg0/cantx1 rg1/cantx2 rg2/canrx rg3 rg4 timer0 ccp1 rf7 re6 re7 re5 re4 re3 re2/cs re0/rd re1/wr lvd porth rh0 rh1 rh2 rh3 rh7/an15:rh4/an12 portk rk0 rk1 rk2 rk3 portj rj0 rj1 rj2 rj3 ra6 pic18cxx8 ds30475a-page 12 advanced information ? 2000 microchip technology inc. table 1-2: pinout i/o descriptions pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description mclr /v pp mclr v pp 716920 i p st master clear (reset) input. this pin is an active low reset to the device. programming voltage input nc ? 1, 18, 35, 52 ? 1, 22, 43, 64 ?? these pins should be left unconnected osc1/clki osc1 clki 39 50 49 62 i i cmos/st cmos oscillator crystal input or external clock source input. st buffer when configured in rc mode. otherwise cmos. external clock source input. always associated with pin function osc1 (see osc1/clki, osc2/clko pins). osc2/clko/ra6 osc2 clko ra6 40 51 50 63 o o i/o ? ? ttl oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate general purpose i/o pin legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) ? 2000 microchip technology inc. advanced information ds30475a-page 13 pic18cxx8 porta is a bi-directional i/o port ra0/an0 ra0 an0 24 34 30 42 i/o i ttl analog digital i/o analog input 0 ra1/an1 ra1 an1 23 33 29 41 i/o i ttl analog digital i/o analog input 1 ra2/an2/v ref - ra2 an2 v ref - 22 32 28 40 i/o i i ttl analog analog digital i/o analog input 2 a/d reference voltage (low) input ra3/an3/v ref + ra3 an3 v ref + 21 31 27 39 i/o i i ttl analog analog digital i/o analog input 3 a/d reference voltage (high) input ra4/t0cki ra4 t0cki 28 39 34 47 i/o i st/od st digital i/o ? open drain when configured as output timer0 external clock input ra5/an4/ss /lvdin ra5 an4 ss lvdin 27 38 33 46 i/o i i i ttl analog st analog digital i/o analog input 4 spi slave select input low voltage detect input ra6 see the osc2/clko/ra6 pin table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) pic18cxx8 ds30475a-page 14 advanced information ? 2000 microchip technology inc. portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 48 60 58 72 i/o i ttl st digital i/o external interrupt 0 rb1/int1 rb1 int1 47 59 57 71 i/o i ttl st digital i/o external interrupt 1 rb2/int2 rb2 int2 46 58 56 70 i/o i ttl st digital i/o external interrupt 2 rb3/int3 rb3 int3 45 57 55 69 i/o i/o ttl st digital i/o external interrupt 3 rb4 44 56 54 68 i/o ttl digital i/o interrupt on change pin rb5 43 55 53 67 i/o ttl digital i/o interrupt-on-change pin rb6 42 54 52 66 i/o i ttl st digital i/o interrupt-on-change pin icsp programming clock rb7 37 48 47 60 i/o i/o ttl st digital i/o interrupt-on-change pin icsp programming data table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) ? 2000 microchip technology inc. advanced information ds30475a-page 15 pic18cxx8 portc is a bi-directional i/o port rc0/t1oso/t13cki rc0 t1oso t13cki 30 41 36 49 i/o o i st ? st digital i/o timer1 oscillator output timer1/timer3 external clock input rc1/t1osi rc1 t1osi 29 40 35 48 i/o i st cmos digital i/o timer1 oscillator input rc2/ccp1 rc2 ccp1 33 44 43 56 i/o i/o st st digital i/o capture1 input/compare1 output/pwm1 output rc3/sck/scl rc3 sck scl 34 45 44 57 i/o i/o i/o st st st digital i/o synchronous serial clock input/output for spi mode synchronous serial clock input/output for i 2 c mode rc4/sdi/sda rc4 sdi sda 35 46 45 58 i/o i i/o st st st digital i/o spi data in i 2 c data i/o rc5/sdo rc5 sdo 36 47 46 59 i/o o st ? digital i/o spi data out rc6/tx/ck rc6 tx ck 31 42 37 50 i/o o i/o st ? st digital i/o usart asynchronous transmit usart synchronous clock (see rx/dt) rc7/rx/dt rc7 rx dt 32 43 38 51 i/o i i/o st st st digital i/o usart asynchronous receive usart synchronous data (see tx/ck) table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) pic18cxx8 ds30475a-page 16 advanced information ? 2000 microchip technology inc. portd is a bi-directional i/o port. these pins have ttl input buffers when external memory is enabled. rd0/psp0 rd0 psp0 583723 i/o i/o st ttl digital i/o parallel slave port data rd1/psp1 rd1 psp1 55 67 69 83 i/o i/o st ttl digital i/o parallel slave port data rd2/psp2 rd2 psp2 54 66 68 82 i/o i/o st ttl digital i/o parallel slave port data rd3/psp3 rd3 psp3 53 65 67 81 i/o i/o st ttl digital i/o parallel slave port data rd4/psp4 rd4 psp4 52 64 66 80 i/o i/o st ttl digital i/o parallel slave port data rd5/psp5 rd5 psp5 51 63 65 79 i/o i/o st ttl digital i/o parallel slave port data rd6/psp6 rd6 psp6 50 62 64 78 i/o i/o st ttl digital i/o parallel slave port data rd7/psp7 rd7 psp7 49 61 63 77 i/o i/o st ttl digital i/o parallel slave port data table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) ? 2000 microchip technology inc. advanced information ds30475a-page 17 pic18cxx8 porte is a bi-directional i/o port re0/rd re0 r d 211415 i/o i st ttl digital i/o read control for parallel slave port (see wr and cs pins) re1/wr re1 w r 110314 i/o i st ttl digital i/o write control for parallel slave port (see cs and rd pins) re2/cs re2 c s 649789 i/o i st ttl digital i/o chip select control for parallel slave port (see rd and wr ) re3 63 8 77 8 i/o st digital i/o re4 62 7 76 7 i/o st digital i/o re5 61 6 75 6 i/o st digital i/o re6 60 5 74 5 i/o st digital i/o re7/ccp2 re7 ccp2 594734 i/o i/o st st digital i/o capture2 input, compare2 output, pwm2 output table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) pic18cxx8 ds30475a-page 18 advanced information ? 2000 microchip technology inc. portf is a bi-directional i/o port rf0/an5 rf0 an5 18 28 24 36 i/o i st analog digital i/o analog input 5 rf1/an6/c2out rf1 an6 c2out 17 27 23 35 i/o i o st analog st digital i/o analog input 6 comparator 2 output rf2/an7/c1out rf2 an7 c1out 16 26 18 30 i/o i o st analog st digital i/o analog input 7 comparator 1 output rf3/an8 rf1 an8 15 25 17 29 i/o i st analog digital i/o analog input 8 rf4/an9 rf1 an9 14 24 16 28 i/o i st analog digital i/o analog input 9 rf5/an10/cv ref rf1 an10 cv ref 13 23 15 27 i/o i o st analog analog digital i/o analog input 10 comparator v ref output rf6/an11 rf6 an11 12 22 14 26 i/o i st analog digital i/o analog input 11 rf7 11 21 13 25 i/o st digital i/o table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) ? 2000 microchip technology inc. advanced information ds30475a-page 19 pic18cxx8 portg is a bi-directional i/o port rg0/cantx1 rg0 cantx1 312516 i/o o st can bus digital i/o can bus output rg1/cantx2 rg1 cantx2 413617 i/o o st can bus digital i/o complimentary can bus output or can bus bit time clock rg2/canrx rg2 canrx 514718 i/o i st can bus digital i/o can bus input rg3 6 15 8 19 i/o st digital i/o rg4 8 17 10 21 i/o st digital i/o porth is a bi-directional i/o port. rh0 ?? 79 10 i/o st digital i/o rh1 ?? 80 11 i/o st digital i/o rh2 ?? 1 12 i/o st digital i/o rh3 ?? 2 13 i/o st digital i/o rh4/an12 rh4 an12 ?? 22 34 i/o i st analog digital i/o analog input 12 rh5/an13 rh5 an13 ?? 21 33 i/o i st analog digital i/o analog input 13 rh6/an14 rh6 an14 ?? 20 32 i/o i st analog digital i/o analog input 14 rh7/an15 rh7 an15 ?? 19 31 i/o i st analog digital i/o analog input 15 table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) pic18cxx8 ds30475a-page 20 advanced information ? 2000 microchip technology inc. portj is a bi-directional i/o port rj0 rj0 rj0 ? ? ? ? 62 ? 76 ? i/o st digital i/o rj1 rj1 rj1 ? ? ? ? 61 ? 75 ? i/o st digital i/o rj2 rj2 rj2 ? ? ? ? 60 ? 74 ? i/o st digital i/o rj3 rj3 rj3 ? ? ? ? 59 ? 73 ? i/o st digital i/o portk is a bi-directional i/o port rk0 ?? 39 52 i/o st digital i/o rk1 ?? 40 53 i/o st digital i/o rk2 ?? 41 54 i/o st digital i/o rk3 ?? 42 55 i/o st digital i/o v ss 9, 25, 41, 56 19, 36, 53, 68 11, 31, 51, 70 23, 44, 65, 84 p ? ground reference for logic and i/o pins v dd 10, 26, 38, 57 2, 20, 37, 49 12, 32, 48, 71 2, 24, 45, 61 p ? positive supply for logic and i/o pins a vss 20 30 26 38 p ? ground reference for analog modules a vdd 19 29 25 37 p ? positive supply for analog modules table 1-2: pinout i/o descriptions (continued) pin name pin number pin type buffer type pic18c658 pic18c858 tqfp plcc tqfp plcc description legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open drain (no p diode to v dd ) ? 2000 microchip technology inc. advanced information ds30475a-page 21 pic18cxx8 2.0 oscillator configurations 2.1 oscillator types the pic18cxx8 can be operated in one of eight oscil- lator modes, programmable by three configuration bits (fosc2, fosc1, and fosc0). 1. lp low power crystal 2. xt crystal/resonator 3. hs high speed crystal/resonator 4. hs4 high speed crystal/resonator with pll enabled 5. rc external resistor/capacitor 6. rcio external resistor/capacitor with i/o pin enabled 7. ec external clock 8. ecio external clock with i/o pin enabled 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hs4 (pll) oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. an external clock source may also be connected to the osc1 pin, as shown in figure 2-3 and figure 2-4. the pic18cxx8 oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (hs, xt or lp osc configuration) note: use of a series cut crystal may give a fre- quency out of the crystal manufacturer ? s specifications. note 1: see table 2-1 and table 2-2 for recom- mended values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the crystal chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18cxx8 r s (2) internal pic18cxx8 ds30475a-page 22 advanced information ? 2000 microchip technology inc. table 2-1: ceramic resonators table 2-2: capacitor selection for crystal oscillator ranges tested: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 68 - 100 pf 15 - 68 pf 15 - 68 pf 68 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 20.0 mhz 25.0 mhz 10 - 68 pf 10 - 22 pf tbd tbd 10 - 68 pf 10 - 22 pf tbd tbd hs+pll 4.0 mhz 8.0 mhz 10.0 mhz tbd 10 - 68 pf tbd tbd 10 - 68 pf tbd these values are for design guidance only. see notes on this page. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. osc type crystal freq cap. range c1 cap. range c2 lp 32.0 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 200 khz 47-68 pf 47-68 pf 1.0 mhz 15 pf 15 pf 4.0 mhz 15 pf 15 pf hs 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 20.0 mhz 15-33 pf 15-33 pf 25.0 mhz tbd tbd hs+pll 4.0 mhz 15 pf 15 pf 8.0 mhz 15-33 pf 15-33 pf 10.0 mhz tbd tbd these values are for design guidance only. see notes on this page. crystals used 32.0 khz epson c-001r32.768k-a 20 ppm 200 khz std xtl 200.000khz 20 ppm 1.0 mhz ecs ecs-10-13-1 50 ppm 4.0 mhz ecs ecs-40-20-1 50 ppm 8.0 mhz epson ca-301 8.000m-c 30 ppm 20.0 mhz epson ca-301 20.000m-c 30 ppm note 1: recommended values of c1 and c2 are identical to the ranges tested (table 2-1). 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: rs may be required in hs mode, as well as xt mode, to avoid overdriving crystals with low drive level specification. ? 2000 microchip technology inc. advanced information ds30475a-page 23 pic18cxx8 2.3 rc oscillator for timing insensitive applications, the ? rc ? and "rcio" device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) val- ues and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 2-2 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-2: rc oscillator mode the rcio oscillator mode functions like the rc mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). 2.4 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. the feedback device between osc1 and osc2 is turned off in these modes to save current. there is no oscilla- tor start-up time required after a power-on reset or after a recovery from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec osc configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-4 shows the pin connections for the ecio oscillator mode. figure 2-4: external clock input operation (ecio configuration) osc2/clko/ra6 c ext r ext pic18cxx8 osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20pf or i/o osc1 osc2 f osc /4 clock from ext. system pic18cxx8 osc1 i/o (osc2) ra6 clock from ext. system pic18cxx8 pic18cxx8 ds30475a-page 24 advanced information ? 2000 microchip technology inc. 2.5 hs4 (pll) a phase locked loop circuit is provided as a pro- grammable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. for an input clock frequency of 10 mhz, the internal clock frequency will be multiplied to 40 mhz. this is useful for customers who are concerned with emi due to high frequency crystals. the pll can only be enabled when the oscillator con- figuration bits are programmed for hs mode. if they are programmed for any other mode, the pll is not enabled and the system clock will come directly from osc1. the pll is one of the modes of the fosc2:fosc0 configuration bits. the oscillator mode is specified dur- ing device programming. a pll lock timer is used to ensure that the pll has locked before device execution starts. the pll lock timer has a time-out referred to as t pll . figure 2-5: pll block diagram mux vco loop filter divide by 4 crystal osc osc2 osc1 f in f out sysclk phase comparator fosc2:fosc0 = ? 110 ? ? 2000 microchip technology inc. advanced information ds30475a-page 25 pic18cxx8 2.6 oscillator switching feature the pic18cxx8 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. for the pic18cxx8 devices, this alternate clock source is the timer1 oscillator. if a low frequency crys- tal (32 khz, for example) has been attached to the timer1 oscillator pins and the timer1 oscillator has been enabled, the device can switch to a low power execution mode. figure 2-6 shows a block diagram of the system clock sources. the clock switching feature is enabled by programming the oscillator switching enable (oscsen ) bit in configuration register config1h to a ? 0 ? . clock switching is disabled in an erased device. see section 9 for further details of the timer1 oscillator. see section 22.0 for configuration register details. 2.6.1 system clock switch bit the system clock source switching is performed under software control. the system clock switch bit, scs (osccon register), controls the clock switching. when the scs bit is ? 0 ? , the system clock source comes from the main oscillator selected by the fosc2:fosc0 con- figuration bits. when the scs bit is set, the system clock source will come from the timer1 oscillator. the scs bit is cleared on all forms of reset. figure 2-6: device clock sources register 2-1: osccon register note: the timer1 oscillator must be enabled to switch the system clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control register (t1con). if the timer1 oscillator is not enabled, any write to the scs bit will be ignored (scs bit forced cleared) and the main oscillator will continue to be the sys- tem clock source. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 ? ? ? ? ? ? ? scs bit 7 bit 0 bit 7-1 unimplemented: read as '0' bit 0 scs: system clock switch bit when oscsen configuration bit = ? 0 ? and t1oscen bit is set: 1 = switch to timer1 oscillator/clock pin 0 = use primary oscillator/clock input pin when oscsen is clear or t1oscen is clear: bit is forced clear legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 t osc 4 x pll t t 1 p t sclk clock source mux tosc/4 timer 1 oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep main oscillator note: i/o pins have diode protection to v dd and v ss . pic18cxx8 ds30475a-page 26 advanced information ? 2000 microchip technology inc. 2.6.2 oscillator transitions the pic18cxx8 devices contain circuitry to prevent "glitches" when switching between oscillator sources. essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. a timing diagram indicating the transition from the main oscillator to the timer1 oscillator is shown in figure 2-7. the timer1 oscillator is assumed to be running all the time. after the scs bit is set, the pro- cessor is frozen at the next occurring q1 cycle. after eight synchronization cycles are counted from the timer1 oscillator, operation resumes. no additional delays are required after the synchronization cycles. the sequence of events that takes place when switch- ing from the timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. in addition to eight clock cycles of the main oscillator, additional delays may take place. if the main oscillator is configured for an external crys- tal (hs, xt, lp), the transition will take place after an oscillator start-up time (t ost ) has occurred. a timing diagram indicating the transition from the timer1 oscil- lator to the main oscillator for hs, xt and lp modes is shown in figure 2-8. figure 2-7: timing diagram for transition from osc1 to timer1 oscillator figure 2-8: timing diagram for transition between timer1 and osc1 (hs,xt,lp) q3 q2 q1 q4 q3 q2 osc1 internal scs (osccon<0>) program pc + 2 pc note 1: delay on internal system clock is eight oscillator cycles for synchronization. q1 t1osi q4 q1 pc + 4 q1 ts cs clock counter system q2 q3 q4 q1 t dly t t 1 p t osc 2 1 34 5678 q3 q3 q4 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: t ost = 1024t osc (drawing not to scale). t1osi clock osc2 t ost q1 pc + 4 t t 1 p t osc t scs 1 234 567 8 ? 2000 microchip technology inc. advanced information ds30475a-page 27 pic18cxx8 if the main oscillator is configured for hs4 (pll) mode, an oscillator start-up time (t ost ) plus an additional pll time-out (t pll ) will occur. the pll time-out is typically 2 ms and allows the pll to lock to the main oscillator frequency. a timing diagram indicating the transition from the timer1 oscillator to the main oscillator for hs4 mode is shown in figure 2-9. if the main oscillator is configured in the rc, rcio, ec or ecio modes, there is no oscillator start-up time-out. operation will resume after eight cycles of the main oscillator have been counted. a timing diagram indicat- ing the transition from the timer1 oscillator to the main oscillator for rc, rcio, ec and ecio modes is shown in figure 2-10. figure 2-9: timing for transition between timer1 and osc1 (hs with pll) figure 2-10: timing for transition between timer1 and osc1 (rc, ec) q4 q1 q1 q2 q3 q4 q1 q2 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: t ost = 1024t osc (drawing not to scale). t1osi clock t ost q3 pc + 4 t pll t osc t t 1 p t scs q4 osc2 pll clock input 1 234 5678 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 osc1 internal system scs (osccon<0>) program counter pc pc + 2 note 1: rc oscillator mode assumed. pc + 4 t1osi clock osc2 q4 t t 1 p t osc t scs 1 23 45 6 78 pic18cxx8 ds30475a-page 28 advanced information ? 2000 microchip technology inc. 2.7 effects of sleep mode on the on -c hip oscillator when the device executes a sleep instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (q1 state). with the oscillator off, the osc1 and osc2 signals will stop oscillating. since all the transistor switching currents have been removed, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the user can wake from sleep through external reset, watchdog timer reset or through an interrupt. 2.8 power-up delays power up delays are controlled by two timers, so that no external reset circuitry is required for most appli- cations. the delays ensure that the device is kept in reset until the device power supply and clock are sta- ble. for additional information on reset operation, see section 3.0 reset. the first timer is the power-up timer (pwrt), which optionally provides a fixed delay of t pwrt (parameter #33) on power-up only (por and bor). the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. with the pll enabled (hs4 oscillator mode), the time-out sequence following a power-on reset is differ- ent from other oscillator modes. the time-out sequence is as follows: the pwrt time-out is invoked after a por time delay has expired, then the oscillator start-up timer (ost) is invoked. however, this is still not a suf- ficient amount of time to allow the pll to lock at high frequencies. the pwrt timer is used to provide an additional time-out. this time is called t pll (parameter #7) to allow the pll ample time to lock to the incoming clock frequency. table 2-3: osc1 and osc2 pin states in sleep mode osc mode osc1 pin osc2 pin rc floating, external resistor should pull high at logic low rcio floating, external resistor should pull high configured as porta, bit 6 ecio floating configured as porta, bit 6 ec floating at logic low lp, xt, and hs feedback inverter disabled, at quiescent voltage level feedback inverter disabled, at quiescent voltage level note: see table 3-1 in section 3.0 reset, for time-outs due to sleep and mclr reset. ? 2000 microchip technology inc. advanced information ds30475a-page 29 pic18cxx8 3.0 reset the pic18cxx8 differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) watchdog timer (wdt) reset (during normal operation) e) programmable brown-out reset (pbor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ? reset ? state on power-on reset, mclr , wdt reset, brown-out reset, mclr reset during sleep and by the reset instruction. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor are set or cleared differently in different reset situations, as indicated in table 3-2. these bits are used in software to determine the nature of the reset. see table 3-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 3-1. the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. a wdt reset does not drive mclr pin low. figure 3-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 v dd rise detect ost/pwrt on-chip rc osc (1) wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 10-bit ripple counter reset enable ost (2) enable pwrt sleep note 1: this is a separate oscillator from the rc oscillator of the clki pin. 2: see table 3-1 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset wdt module pic18cxx8 ds30475a-page 30 advanced information ? 2000 microchip technology inc. 3.1 power- o n r e set (por) a power-on reset pulse is generated on-chip when a v dd rise is detected. to take advantage of the por cir- cuitry, connect the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc compo- nents usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (param- eter d004). for a slow rise time, see figure 3-2. when the device starts normal operation (exits the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. brown-out reset may be used to meet the voltage start-up condition. figure 3-2: external power-on reset circuit (for slow v dd power-up) 3.2 power-up timer (pwrt) the power-up timer provides a fixed nominal time-out (parameter #33), only on power-up from the por. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as the pwrt is active. the pwrt ? s time delay allows v dd to rise to an acceptable level. a configuration bit (pwrten in config2l register) is provided to enable/disable the pwrt. the power-up time delay will vary from chip to chip due to v dd , temperature and process variation. see dc parameter #33 for details. 3.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #32). this ensures that the crystal oscillator or resonator has started and stabi- lized. the ost time-out is invoked only for xt, lp, hs and hs4 modes and only on power-on reset or wake-up from sleep. 3.4 pll lock time-out with the pll enabled, the time-out sequence following a power-on reset is different from other oscillator modes. a portion of the power-up timer is used to pro- vide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out (ost). 3.5 brown- ou t r e set (bor) a configuration bit, boren, can disable (if clear/programmed) or enable (if set) the brown-out reset circuitry. if v dd falls below parameter d005 for greater than parameter #35, the brown-out situation resets the chip. a reset may not occur if v dd falls below parameter d005 for less than parameter #35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will then be invoked and will keep the chip in reset an additional time delay (parameter #33). if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will execute the additional time delay. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device ? s electrical specification. 3: r1 = 100 ? to 1 k ? will limit any current flowing into mclr from external capacitor c in the event of mclr/ v pp pin break- down due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18cxx8 ? 2000 microchip technology inc. advanced information ds30475a-page 31 pic18cxx8 3.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time-out is invoked after the por time delay has expired, then ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 3-3, figure 3-4, figure 3-5, figure 3-6 and figure 3-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. bringing mclr high will begin execution immediately (figure 3-5). this is useful for testing purposes or to synchronize more than one pic18cxx8 device operat- ing in parallel. table 3-2 shows the reset conditions for some spe- cial function registers, while table 3-3 shows the reset conditions for all registers. table 3-1: time-out in various situations register 3-1: rcon register bits and positions table 3-2: status bits, their significance and the initialization condition for rcon register oscillator configuration power-up (2) brown-out (2) wake-up from sleep or oscillator switch pwrte n = 0 pwrten = 1 hs with pll enabled (1) 72 ms + 1024tosc + 2 ms 1024tosc + 2 ms 72 ms + 1024tosc + 2 ms 1024tosc + 2 ms hs, xt, lp 72 ms + 1024tosc 1024tosc 72 ms + 1024tosc 1024tosc ec 72 ms ? 72 ms ? external rc 72 ms ? 72 ms ? note 1: 2 ms = nominal time required for the 4x pll to lock. 2: 72 ms is the nominal power-up timer delay. r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ipen lwrt ? ri to pd por bor bit 7 bit 0 condition program counter rcon register ri to pd por bor stkful stkunf power-on reset 0000h 00-1 1100 1 1 1 0 0 u u mclr reset during normal operation 0000h 00-u uuuu u u u u u u u software reset during normal operation 0000h 0u-0 uuuu 0 u u u u u u stack full reset during normal operation 0000h 0u-u uu11 u u u 1 1 u 1 stack underflow reset during normal operation 0000h 0u-u uu11 u u u 1 1 1 u mclr reset during sleep 0000h 00-u 10uu u 1 0 u u u u wdt reset 0000h 0u-u 01uu u 0 1 u u u u wdt wake-up pc + 2 uu-u 00uu u 0 0 u u u u brown-out reset 0000h 0u-1 11u0 1 1 1 u 0 u u interrupt wake-up from sleep pc + 2 (1) uu-u 00uu u 0 0 u u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector ( 0x000008h or 0x000018h ). pic18cxx8 ds30475a-page 32 advanced information ? 2000 microchip technology inc. figure 3-3: time-out sequence on power-up (mclr tied to v dd ) figure 3-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 3-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost ? 2000 microchip technology inc. advanced information ds30475a-page 33 pic18cxx8 figure 3-6: slow rise time (mclr tied to v dd ) figure 3-7: time-out sequence on por w/ pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t deadtime t pwrt t ost v dd mclr iinternal por pwrt time-out ost time-out internal reset pll time-out t pll t ost = 1024 clock cycles. t pll 2 ms max. first three stages of the pwrt timer. pic18cxx8 ds30475a-page 34 advanced information ? 2000 microchip technology inc. table 3-3: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu 658 858 ---0 0000 ---0 0000 ---0 uuuu (3) tosh 658 858 0000 0000 0000 0000 uuuu uuuu (3) tosl 658 858 0000 0000 0000 0000 uuuu uuuu (3) stkptr 658 858 00-0 0000 00-0 0000 uu-u uuuu (3) pclatu 658 858 ---0 0000 ---0 0000 ---u uuuu pclath 658 858 0000 0000 0000 0000 uuuu uuuu pcl 658 858 0000 0000 0000 0000 pc + 2 (2) tblptru 658 858 --00 0000 --00 0000 --uu uuuu tblptrh 658 858 0000 0000 0000 0000 uuuu uuuu tblptrl 658 858 0000 0000 0000 0000 uuuu uuuu tablat 658 858 0000 0000 0000 0000 uuuu uuuu prodh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu prodl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu intcon 658 858 0000 000x 0000 000u uuuu uuuu (1) intcon2 658 858 1111 1111 1111 1111 uuuu uuuu (1) intcon3 658 858 1100 0000 1100 0000 uuuu uuuu (1) indf0 658 858 n/a n/a n/a postinc0 658 858 n/a n/a n/a postdec0 658 858 n/a n/a n/a preinc0 658 858 n/a n/a n/a plusw0 658 858 n/a n/a n/a fsr0h 658 858 ---- 0000 ---- 0000 ---- uuuu fsr0l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu wreg 658 858 xxxx xxxx uuuu uuuu uuuu uuuu indf1 658 858 n/a n/a n/a postinc1 658 858 n/a n/a n/a postdec1 658 858 n/a n/a n/a preinc1 658 858 n/a n/a n/a plusw1 658 858 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. ? 2000 microchip technology inc. advanced information ds30475a-page 35 pic18cxx8 fsr1h 658 858 ---- 0000 ---- 0000 ---- uuuu fsr1l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu bsr 658 858 ---- 0000 ---- 0000 ---- uuuu indf2 658 858 n/a n/a n/a postinc2 658 858 n/a n/a n/a postdec2 658 858 n/a n/a n/a preinc2 658 858 n/a n/a n/a plusw2 658 858 n/a n/a n/a fsr2h 658 858 ---- 0000 ---- 0000 ---- uuuu fsr2l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu status 658 858 ---x xxxx ---u uuuu ---u uuuu tmr0h 658 858 xxxx xxxx uuuu uuuu uuuu uuuu tmr0l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu t0con 658 858 1111 1111 1111 1111 uuuu uuuu osccon 658 858 ---- ---0 ---- ---0 ---- ---u lvdcon 658 858 --00 0101 --00 0101 --uu uuuu wdtcon 658 858 ---- ---0 ---- ---0 ---- ---u rcon (4, 6) 658 858 00-1 11q0 00-1 qquu uu-u qquu tmr1h 658 858 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu t1con 658 858 0-00 0000 u-uu uuuu u-uu uuuu tmr2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu pr2 658 858 1111 1111 1111 1111 1111 1111 t2con 658 858 -000 0000 -000 0000 -uuu uuuu sspbuf 658 858 xxxx xxxx uuuu uuuu uuuu uuuu sspadd 658 858 0000 0000 0000 0000 uuuu uuuu sspstat 658 858 0000 0000 0000 0000 uuuu uuuu sspcon1 658 858 0000 0000 0000 0000 uuuu uuuu sspcon2 658 858 0000 0000 0000 0000 uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. pic18cxx8 ds30475a-page 36 advanced information ? 2000 microchip technology inc. adresh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu adresl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 658 858 --00 0000 --00 0000 --uu uuuu adcon1 658 858 --00 0000 --00 0000 --uu uuuu adcon2 658 858 0--- -000 0--- -000 u--- -uuu ccpr1h 658 858 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 658 858 --00 0000 --00 0000 --uu uuuu ccpr2h 658 858 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 658 858 --00 0000 --00 0000 --uu uuuu cvrcon 658 858 0000 0000 0000 0000 uuuu uuuu cmcon 658 858 0000 0000 0000 0000 uuuu uuuu tmr3h 658 858 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 658 858 xxxx xxxx uuuu uuuu uuuu uuuu t3con 658 858 0000 0000 uuuu uuuu uuuu uuuu pspcon 658 858 0000 ---- 0000 ---- uuuu ---- spbrg 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rcreg 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txreg 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txsta 658 858 0000 -01x 0000 -01u uuuu -uuu rcsta 658 858 0000 000x 0000 000u uuuu uuuu ipr3 658 858 1111 1111 1111 1111 uuuu uuuu pir3 658 858 0000 0000 0000 0000 uuuu uuuu pie3 658 858 0000 0000 0000 0000 uuuu uuuu ipr2 658 858 -1-- 1111 -1-- 1111 -u-- uuuu pir2 658 858 -0-- 0000 -0-- 0000 -u-- uuuu (1) pie2 658 858 -0-- 0000 -0-- 0000 -u-- uuuu ipr1 658 858 1111 1111 1111 1111 uuuu uuuu 658 858 -111 1111 -111 1111 -uuu uuuu pir1 658 858 0000 0000 0000 0000 uuuu uuuu (1) 658 858 -000 0000 -000 0000 -uuu uuuu (1) pie1 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 -000 0000 -000 0000 -uuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. ? 2000 microchip technology inc. advanced information ds30475a-page 37 pic18cxx8 trisj (7) -858 1111 1111 1111 1111 uuuu uuuu trish (7) -858 1111 1111 1111 1111 uuuu uuuu trisg 658 858 ---1 1111 ---1 1111 ---u uuuu trisf 658 858 1111 1111 1111 1111 uuuu uuuu trise 658 858 1111 1111 1111 1111 uuuu uuuu trisd 658 858 1111 1111 1111 1111 uuuu uuuu trisc 658 858 1111 1111 1111 1111 uuuu uuuu trisb 658 858 1111 1111 1111 1111 uuuu uuuu trisa (5) 658 858 -111 1111 (5) -111 1111 (5) -uuu uuuu (5) latj (7) -858 xxxx xxxx uuuu uuuu uuuu uuuu lath (7) -858 xxxx xxxx uuuu uuuu uuuu uuuu latg 658 858 ---x xxxx ---u uuuu ---u uuuu latf 658 858 xxxx xxxx uuuu uuuu uuuu uuuu late 658 858 xxxx xxxx uuuu uuuu uuuu uuuu latd 658 858 xxxx xxxx uuuu uuuu uuuu uuuu latc 658 858 xxxx xxxx uuuu uuuu uuuu uuuu latb 658 858 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) 658 858 -xxx xxxx (5) -uuu uuuu (5) -uuu uuuu (5) portj (7) -858 xxxx xxxx uuuu uuuu uuuu uuuu porth (7) -858 0000 xxxx 0000 uuuu uuuu uuuu portg 658 858 ---x xxxx ---u uuuu ---u uuuu portf 658 858 x000 0000 u000 0000 uuuu uuuu porte 658 858 --00 xxxx uuuu u000 uuuu uuuu portd 658 858 xxxx xxxx uuuu uuuu uuuu uuuu portc 658 858 xxxx xxxx uuuu uuuu uuuu uuuu portb 658 858 xxxx xxxx uuuu uuuu uuuu uuuu porta (5) 658 858 -x0x 0000 (5) -u0u 0000 (5) -uuu uuuu (5) trisk 658 858 1111 1111 1111 1111 uuuu uuuu latk 658 858 xxxx xxxx uuuu uuuu uuuu uuuu portk 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txerrcnt 658 858 0000 0000 0000 0000 uuuu uuuu rxerrcnt 658 858 0000 0000 0000 0000 uuuu uuuu comstat 658 858 0000 0000 0000 0000 uuuu uuuu ciocon 658 858 1000 ---- 1000 ---- uuuu ---- brgcon3 658 858 -0-- -000 -0-- -000 -u-- -uuu brgcon2 658 858 0000 0000 0000 0000 uuuu uuuu brgcon1 658 858 0000 0000 0000 0000 uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. pic18cxx8 ds30475a-page 38 advanced information ? 2000 microchip technology inc. cancon 658 858 xxxx xxx- uuuu uuu- uuuu uuu- canstat 658 858 xxx- xxx- uuu- uuu- uuu- uuu- rxb0d7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0d0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0dlc 658 858 0xxx xxxx 0uuu uuuu uuuu uuuu rxb0eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0sidl 658 858 xxxx x-xx uuuu u-uu uuuu u-uu rxb0sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb0con 658 858 000- 0000 000- 0000 uuu- uuuu rxb1d7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1d0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1dlc 658 858 0xxx xxxx 0uuu uuuu uuuu uuuu rxb1eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1sidl 658 858 xxxx x0xx uuuu u0uu uuuu uuuu rxb1sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxb1con 658 858 0000 0000 0000 0000 uuuu uuuu txb0d7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0d6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0d5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0d4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0d3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0d2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0d1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. ? 2000 microchip technology inc. advanced information ds30475a-page 39 pic18cxx8 txb0d0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0dlc 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu txb0eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0sidl 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu txb0sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb0con 658 858 0000 0000 0000 0000 uuuu uuuu txb1d7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1d0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1dlc 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu txb1eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1sidl 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu txb1sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb1con 658 858 0000 0000 0000 0000 uuuu uuuu txb2d7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2d0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2dlc 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu txb2eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2sidl 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu txb2sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu txb2con 658 858 0000 0000 0000 0000 uuuu uuuu rxm1eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxm1eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. pic18cxx8 ds30475a-page 40 advanced information ? 2000 microchip technology inc. rxm1sidl 658 858 xxx- --xx uuu- --uu uuu- --uu rxm1sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxm0eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxm0eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxm0sidl 658 858 xxx- --xx uuu- --uu uuu- --uu rxm0sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf5eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf5eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf5sidl 658 858 xxx- x-xx uuu- u-uu uuu- u-uu rxf5sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf4eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf4eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf4sidl 658 858 xxx- x-xx uuu- u-uu uuu- u-uu rxf4sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf3eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf3eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf3sidl 658 858 xxx- x-xx uuu- u-uu uuu- u-uu rxf3sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf2eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf2eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf2sidl 658 858 xxx- x-xx uuu- u-uu uuu- u-uu rxf2sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf1eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf1eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf1sidl 658 858 xxx- x-xx uuu- u-uu uuu- u-uu rxf1sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf0eidl 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf0eidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu rxf0sidl 658 858 xxx- x-xx uuu- u-uu uuu- u-uu rxf0sidh 658 858 xxxx xxxx uuuu uuuu uuuu uuuu table 3-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr reset wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? , q = value depends on condition note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector ( 0008h or 0018h ). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 3-2 for reset value for specific condition. 5: bit 6 of porta, lata, and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . 6: the long write enable is only reset on a por or mclr . 7: available on pic18c858 only. ? 2000 microchip technology inc. advanced information ds30475a-page 41 pic18cxx8 4.0 memory organization there are two memory blocks in enhanced mcu devices. these memory blocks are: program memory data memory each block has its own bus so that concurrent access can occur. 4.1 program memory organization the pic18cxx8 devices have a 21-bit program counter that is capable of addressing the 2 mbyte program memory space. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. figure 4-1 shows the diagram for program memory map and stack for the pic18c658 and pic18c858. 4.1.1 internal program memory operation all devices have 32 kbytes of internal eprom program memory. this means that the pic18cxx8 devices can store up to 16k of single word instructions. accessing a location between the physically implemented mem- ory and the 2 mbyte address will cause a read of all '0's (a nop instruction). figure 4-1: program memory map and stack for pic18c658/858 pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? 21 0000h 0018h 8000h 7fffh on-chip program memory high priority interrupt vector 0008h user memory space read ? 1 ? 1fffffh pic18cxx8 ds30475a-page 42 advanced information ? 2000 microchip technology inc. 4.2 r eturn address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a push, call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruc- tion. pclatu and pclath are not affected by any of the return instructions. the stack operates as a 31 word by 21-bit stack mem- ory and a 5-bit stack pointer, with the stack pointer ini- tialized to 00000b after all resets. there is no ram associated with stack pointer 00000b. this is only a reset value. during a call type instruction causing a push onto the stack, the stack pointer is first incre- mented and the ram location pointed to by the stack pointer is written with the contents of the pc. during a return type instruction causing a pop from the stack, the contents of the ram location indicated by the stkptr is transferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable, and the data on the top of the stack is readable and writable through sfr registers. status bits indicate if the stack pointer is at or beyond the 31 levels provided. 4.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl allow access to the contents of the stack location indicated by the stkptr register. this allows users to imple- ment a software stack if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user should disable the global interrupt enable bits during this time to prevent inadvertent stack opera- tions. 4.2.2 return stack pointer (stkptr) the stkptr register contains the stack pointer value, the stkful (stack full) status bit, and the stkunf (stack underflow) status bits. register 4-1 shows the stkptr register. the value of the stack pointer can be 0 through 31. the stack pointer increments when val- ues are pushed onto the stack and decrements when values are popped off the stack. at reset, the stack pointer value will be 0. the user may read and write the stack pointer value. this feature can be used by a real time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit can only be cleared in software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. refer to section 18 for a description of the device configuration bits. if stvren is set (default) the 31st push will push the (pc + 2) value onto the stack, set the stkful bit, and reset the device. the stkful bit will remain set and the stack pointer will be set to 0. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. the 32nd push will overwrite the 31st push (and so on), while stkptr remains at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at 0. the stkunf bit will remain set until cleared in software or a por occurs. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appro- priate actions can be taken. ? 2000 microchip technology inc. advanced information ds30475a-page 43 pic18cxx8 register 4-1: stkptr - stack pointer register figure 4-2: return address stack and associated registers r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 stkful : stack full flag bit 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf : stack underflow flag bit 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented : read as '0' bit 4-0 sp4:sp0 : stack pointer location bits note: bit 7 and bit 6 can only be cleared in user software or by a por. legend r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared c = clearable bit 00011 0x001a34 11111 11110 11101 00010 00001 00000 (1) 00010 return address stack top-of-stack 0x000d58 tosl tosh tosu 0x34 0x1a 0x00 stkptr<4:0> 0x000000 note 1: no ram associated with this address; always maintained ? 0 ? s. pic18cxx8 ds30475a-page 44 advanced information ? 2000 microchip technology inc. 4.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execu- tion is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the cur- rent pc value onto the stack. tosu, tosh and tosl can then be modified to place a return address on the stack. the pop instruction discards the current tos by decre- menting the stack pointer. the previous value pushed onto the stack then becomes the tos value. 4.2.4 stack full/underflow resets these resets are enabled by programming the stvren configuration bit. when the stvren bit is disabled, a full or underflow condition will set the appro- priate stkful or stkunf bit, but not cause a device reset. when the stvren bit is enabled, a full or underflow will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are only cleared by the user software or a por. 4.3 fast register stack a ? fast return ? option is available for interrupts and calls. a fast register stack is provided for the status, wreg and bsr registers and is only one layer in depth. the stack is not readable or writable and is loaded with the current value of the corresponding reg- ister when the processor vectors for an interrupt. the values in the fast register stack are then loaded back into the working registers if the fast return instruc- tion is used to return from the interrupt. a low or high priority interrupt source will push values into the stack registers. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority inter- rupt will be overwritten. if high priority interrupts are not disabled during low pri- ority interrupts, users must save the key registers in software during a low priority interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a fast call instruction must be executed. example 4-1 shows a source code example that uses the fast register stack. example 4-1: fast register stack code example call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? ? return fast ;restore values saved ;in fast register stack ? 2000 microchip technology inc. advanced information ds30475a-page 45 pic18cxx8 4.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21-bits wide. the low byte is called the pcl register. this reg- ister is readable and writable. the high byte is called the pch register. this register contains the pc<15:8> bits and is not directly readable or writable. updates to the pch register may be performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of pcl is fixed to a value of ? 0 ? . the pc increments by 2 to address sequential instruc- tions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. the contents of pclath and pclatu will be trans- ferred to the program counter by an operation that writes pcl. similarly, the upper two bytes of the pro- gram counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 4.8.1). 4.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 4-3. figure 4-3: clock/instruction cycle q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+2 pc+4 fetch inst (pc) execute inst (pc-2) fetch inst (pc+2) execute inst (pc) fetch inst (pc+4) execute inst (pc+2) internal phase clock pic18cxx8 ds30475a-page 46 advanced information ? 2000 microchip technology inc. 4.6 instruction flow/pipelining an ? instruction cycle ? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), two cycles are required to complete the instruction (example 4-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ? instruction register ? (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). 4.7 i nstructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = ? 0 ? ). figure 4-1 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 4.4). the call and goto instructions have an absolute pro- gram memory address embedded into the instruction. since instructions are always stored on word bound- aries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 4-1 shows how the instruction ? goto 000006h ? is encoded in the program memory. program branch instructions that encode a rel- ative address offset operate in the same manner. the offset value stored in a branch instruction represents the number of single word instructions by which the pc will be offset. section 23.0 provides further details of the instruction set. example 4-2: instruction pipeline flow table 4-1: instructions in program memory all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ? flushed ? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1 instruction opcode memory address ? 000007h movlw 055h 0e55h 55h 000008h 0eh 000009h goto 000006h ef03h, f000h 03h 00000ah efh 00000bh 00h 00000ch f0h 00000dh movff 123h, 456h c123h, f456h 23h 00000eh c1h 00000fh 56h 000010h f4h 000011h ? 000012h ? 2000 microchip technology inc. advanced information ds30475a-page 47 pic18cxx8 4.7.1 two word instructions the pic18cxx8 devices have 4 two word instructions: movff, call, goto and lfsr . the second word of these instructions has the 4 msb ? s set to 1 ? s and is a special kind of nop instruction. the lower 12 bits of the second word contain data to be used by the instruction. if the first word of the instruction is executed, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is neces- sary when the two word instruction is preceded by a conditional instruction that changes the pc. a program example that demonstrates this concept is shown in example 4-3. refer to section 19.0 for further details of the instruction set. 4.8 lookup tables lookup tables are implemented two ways. these are: computed goto table reads 4.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). a lookup table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table before exe- cuting a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruc- tion executed will be one of the retlw 0xnn instruc- tions that returns the value 0xnn to the calling function. the offset value (value in wreg) specifies the number of bytes that the program counter should advance. in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. 4.8.2 table reads/table writes a better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. lookup table data may be stored as 2 bytes per pro- gram word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to, program memory. data is trans- ferred to/from program memory one byte at a time. a description of the table read/table write operation is shown in section 5.0. example 4-3: two word instructions warning: the lsb of pcl is fixed to a value of ? 0 ? . hence, computed goto to an odd address is not possible. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, execute 2-word instruction 1111 0100 0101 0110 ; 2nd operand holds address of reg2 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes 1111 0100 0101 0110 ; 2nd operand becomes nop 0010 0100 0000 0000 addwf reg3 ; continue code pic18cxx8 ds30475a-page 48 advanced information ? 2000 microchip technology inc. 4.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 4-4 shows the data memory organization for the pic18cxx8 devices. the data memory map is divided into as many as 16 banks that contain 256 bytes each. the lower 4 bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits for the bsr are not implemented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfr ? s are used for control and status of the controller and peripheral functions, while gpr ? s are used for data storage and scratch pad operations in the user ? s appli- cation. the sfr ? s start at the last location of bank 15 (0xfff) and grow downwards. gpr ? s start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ? 0 ? s. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of the file select register (fsr). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing or by the use of the movff instruction. the movff instruction is a two word/two cycle instruction that moves a value from one register to another. to ensure that commonly used registers (sfr ? s and select gpr ? s) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 4.10 pro- vides a detailed description of the access ram. 4.9.1 general purpose register file the register file can be accessed either directly or indi- rectly. indirect addressing operates through the file select registers (fsr). the operation of indirect addressing is shown in section 4.12. enhanced mcu devices may have banked memory in the gpr area. gpr ? s are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. bank 15 (0xf00 to 0xfff) contains sfr ? s. all other banks of data memory contain gpr registers starting with bank 0. 4.9.2 special function registers the special function registers (sfr ? s) are registers used by the cpu and peripheral modules for control- ling the desired operation of the device. these regis- ters are implemented as static ram. a list of these registers is given in table 4-2. the sfr ? s can be classified into two sets: those asso- ciated with the ? core ? function and those related to the peripheral functions. those registers related to the ? core ? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfr ? s are typically distributed among the peripher- als whose functions they control. the unused sfr locations will be unimplemented and read as '0's. see table 4-2 for addresses for the sfr ? s. ? 2000 microchip technology inc. advanced information ds30475a-page 49 pic18cxx8 figure 4-4: data memory map for pic18c658/858 bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000b = 0001b = 1110b = 1111b 060h 05fh f60h fffh 00h 5fh 60h ffh access bank bank 4 bank 3 bank 2 f5fh f00h effh 3ffh 300h 2ffh 200h 1ffh 100h 0ffh 000h = 0110b = 0101b = 0011b = 0010b access gpr ? s ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h gpr ? s gpr ? s gpr ? s gpr ? s access sfr ? s sfr ? s access bank high access bank low bank 5 gpr ? s gpr ? s bank 6 to 4ffh 400h 5ffh 500h 600h unused read ? 00h ? = 0100b (sfr ? s) when a = 0, the bsr is ignored and the access bank is used. the first 96 bytes are gen- eral purpose ram (from bank 0). the next 160 bytes are special function registers (from bank 15). when a = 1, the bsr is used to specify the ram location that the instruction uses. (gpr ? s) pic18cxx8 ds30475a-page 50 advanced information ? 2000 microchip technology inc. table 4-2: special function register map address name address name address name address name fffh tosu fdfh indf2 (2) fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 (2) fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 (2) fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 (2) fbch ccpr2h f9ch ? ffbh pclatu fdbh plusw2 (2) fbbh ccpr2l f9bh ? ffah pclath fdah fsr2h fbah ccp2con f9ah trisj (5) ff9h pcl fd9h fsr2l fb9h ? f99h trish (5) ff8h tblptru fd8h status fb8h ? f98h trisg ff7h tblptrh fd7h tmr0h fb7h ? f97h trisf ff6h tblptrl fd6h tmr0l fb6h ? f96h trise ff5h tablat fd5h t0con fb5h cvrcon f95h trisd ff4h prodh fd4h ? fb4h cmcon f94h trisc ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj (5) ff0h intcon3 fd0h rcon fb0h pspcon f90h lath (5) fefh indf0 (2) fcfh tmr1h fafh spbrg f8fh latg feeh postinc0 (2) fceh tmr1l faeh rcreg f8eh latf fedh postdec0 (2) fcdh t1con fadh txreg f8dh late fech preinc0 (2) fcch tmr2 fach txsta f8ch latd febh plusw0 (2) fcbh pr2 fabh rcsta f8bh latc feah fsr0h fcah t2con faah ? f8ah latb fe9h fsr0l fc9h sspbuf fa9h ? f89h lata fe8h wreg fc8h sspadd fa8h ? f88h portj (5) fe7h indf1 (2) fc7h sspstat fa7h ? f87h porth (5) fe6h postinc1 (2) fc6h sspcon1 fa6h ? f86h portg fe5h postdec1 (2) fc5h sspcon2 fa5h ipr3 f85h portf fe4h preinc1 (2) fc4h adresh fa4h pir3 f84h porte fe3h plusw1 (2) fc3h adresl fa3h pie3 f83h portd fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h adcon2 fa0h pie2 f80h porta note 1: unimplemented registers are read as ? 0 ? . 2: this is not a physical register. 3: contents of register is dependent on win2:win0 bits in cancon register. 4: canstat register is repeated in these locations to simplify application firmware. unique names are given for each instance of the canstat register due to the microchip header file requirement. 5: available on pic18c858 only. ? 2000 microchip technology inc. advanced information ds30475a-page 51 pic18cxx8 f7fh trisk (5) f5fh ? f3fh ? f1fh rxm1eid0 f7eh latk (5) f5eh canstatro0 (4) f3eh canstatro2 (4) f1eh rxm1eid8 f7dh portk (5) f5dh rxb1d7 f3dh txb1d7 f1dh rxm1sidl f7ch ? f5ch rxb1d6 f3ch txb1d6 f1ch rxm1sidh f7bh ? f5bh rxb1d5 f3bh txb1d5 f1bh rxm0eid0 f7ah ? f5ah rxb1d4 f3ah txb1d4 f1ah rxm0eid8 f79h ? f59h rxb1d3 f39h txb1d3 f19h rxm0sidl f78h ? f58h rxb1d2 f38h txb1d2 f18h rxm0sidh f77h ? f57h rxb1d1 f37h txb1d1 f17h rxf5eid0 f76h txerrcnt f56h rxb1d0 f36h txb1d0 f16h rxf5eid8 f75h rxerrcnt f55h rxb1dlc f35h txb1dlc f15h rxf5sidl f74h comstat f54h rxb1eidl f34h txb1eidl f14h rxf5sidh f73h ciocon f53h rxb1eidh f33h txb1eidh f13h rxf4eid0 f72h brgcon3 f52h rxb1sidl f32h txb1sidl f12h rxf4eid8 f71h brgcon2 f51h rxb1sidh f31h txb1sidh f11h rxf4sidl f70h brgcon1 f50h rxb1con f30h txb1con f10h rxf4sidh f6fh cancon f4fh ? f2fh ? f0fh rxf3eid0 f6eh canstat f4eh canstatro1 (4) f2eh canstatro3 (4) f0eh rxf3eid8 f6dh rxb0d7 (3) f4dh txb0d7 f2dh txb2d7 f0dh rxf3sidl f6ch rxb0d6 (3) f4ch txb0d6 f2ch txb2d6 f0ch rxf3sidh f6bh rxb0d5 (3) f4bh txb0d5 f2bh txb2d5 f0bh rxf2eid0 f6ah rxb0d4 (3) f4ah txb0d4 f2ah txb2d4 f0ah rxf2eid8 f69h rxb0d3 (3) f49h txb0d3 f29h txb2d3 f09h rxf2sidl f68h rxb0d2 (3) f48h txb0d2 f28h txb2d2 f08h rxf2sidh f67h rxb0d1 (3) f47h txb0d1 f27h txb2d1 f07h rxf1eid0 f66h rxb0d0 (3) f46h txb0d0 f26h txb2d0 f06h rxf1eid8 f65h rxb0dlc (3) f45h txb0dlc f25h txb2dlc f05h rxf1sidl f64h rxb0eidl (3) f44h txb0eidl f24h txb2eidl f04h rxf1sidh f63h rxb0eidh (3) f43h txb0eidh f23h txb2eidh f03h rxf0eidl f62h rxb0sidl (3) f42h txb0sidl f22h txb2sidl f02h rxf0eidh f61h rxb0sidh (3) f41h txb0sidh f21h txb2sidh f01h rxf0sidl f60h rxb0con (3) f40h txb0con f20h txb2con f00h rxf0sidh note: shaded registers are available in bank 15, while the rest are in access bank low. address name address name address name address name note 1: unimplemented registers are read as ? 0 ? . 2: this is not a physical register. 3: contents of register is dependent on win2:win0 bits in cancon register. 4: canstat register is repeated in these locations to simplify application firmware. unique names are given for each instance of the canstat register due to the microchip header file requirement. 5: available on pic18c858 only. pic18cxx8 ds30475a-page 52 advanced information ? 2000 microchip technology inc. table 4-3: register file summary filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 ---0 0000 tosh top-of-stack high byte (tos<15:8>) 0000 0000 0000 0000 tosl top-of-stack low byte (tos<7:0>) 0000 0000 0000 0000 stkptr stkful stkunf ? return stack pointer 00-0 0000 00-0 0000 pclatu ? ? bit 21 (3) holding register for pc<20:16> --00 0000 --00 0000 pclath holding register for pc<15:8> 0000 0000 0000 0000 pcl pc low byte (pc<7:0>) 0000 0000 0000 0000 tblptru ? ? bit 21 (2) program memory table pointer upper byte (tblptr<20:16>) ---0 0000 ---0 0000 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 0000 0000 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 0000 0000 tablat program memory table latch 0000 0000 0000 0000 prodh product register high byte xxxx xxxx uuuu uuuu prodl product register low byte xxxx xxxx uuuu uuuu intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 1111 1111 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 1100 0000 indf0 uses contents of fsr0 to address data memory - value of fsr0 not changed (not a physical register) n/a n/a postinc0 uses contents of fsr0 to address data memory - value of fsr0 post-incremented (not a physical register) n/a n/a postdec0 uses contents of fsr0 to address data memory - value of fsr0 post-decremented (not a physical register) n/a n/a preinc0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) n/a n/a plusw0 uses contents of fsr0 to address data memory - value of fsr0 pre-incremented (not a physical register) - value of fsr0 offset by wreg n/a n/a fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- 0000 ---- 0000 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx uuuu uuuu wreg working register xxxx xxxx uuuu uuuu indf1 uses contents of fsr1 to address data memory - value of fsr1 not changed (not a physical register) n/a n/a postinc1 uses contents of fsr1 to address data memory - value of fsr1 post-incremented (not a physical register) n/a n/a postdec1 uses contents of fsr1 to address data memory - value of fsr1 post-decremented (not a physical register) n/a n/a preinc1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) n/a n/a plusw1 uses contents of fsr1 to address data memory - value of fsr1 pre-incremented (not a physical register) - value of fsr1 offset by wreg n/a n/a fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- 0000 ---- 0000 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx uuuu uuuu bsr ? ? ? ? bank select register ---- 0000 ---- 0000 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. ? 2000 microchip technology inc. advanced information ds30475a-page 53 pic18cxx8 indf2 uses contents of fsr2 to address data memory - value of fsr2 not changed (not a physical register) n/a n/a postinc2 uses contents of fsr2 to address data memory - value of fsr2 post-incremented (not a physical register) n/a n/a postdec2 uses contents of fsr2 to address data memory - value of fsr2 post-decremented (not a physical register) n/a n/a preinc2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) n/a n/a plusw2 uses contents of fsr2 to address data memory - value of fsr2 pre-incremented (not a physical register) - value of fsr2 offset by wreg n/a n/a fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- 0000 ---- 0000 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx uuuu uuuu status ? ? ? novz dcc ---x xxxx ---u uuuu tmr0h timer0 register high byte 0000 0000 0000 0000 tmr0l timer0 register low byte xxxx xxxx uuuu uuuu t0con tmr0on t08bit t0cs t0se t0ps3 t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 osccon ? ? ? ? ? ? ? scs ---- ---0 ---- ---0 lvdcon ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 --00 0101 wdtcon ? ? ? ? ? ? ? swdten ---- ---0 ---- ---0 rcon ipen lwrt ? ri to pd por bor 00-1 11qq 00-q qquu tmr1h timer1 register high byte xxxx xxxx uuuu uuuu tmr1l timer1 register low byte xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu tmr2 timer2 register 0000 0000 0000 0000 pr2 timer2 period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 sspbuf ssp receive buffer/transmit register xxxx xxxx uuuu uuuu sspadd ssp address register in i 2 c slave mode. ssp baud rate reload register in i 2 c master mode. 0000 0000 0000 0000 sspstat smp cke d/a psr/w ua bf 0000 0000 0000 0000 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 adresh a/d result register high byte xxxx xxxx uuuu uuuu adresl a/d result register low byte xxxx xxxx uuuu uuuu adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 --00 0000 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 -000 0000 -000 0000 adcon2 adfm ? ? ? ? adcs2 adcs1 adcs0 0--- -000 0--- -000 filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. pic18cxx8 ds30475a-page 54 advanced information ? 2000 microchip technology inc. ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccpm3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2h capture/compare/pwm register 2 high byte xxxx xxxx uuuu uuuu ccpr2l capture/compare/pwm register 2 low byte xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccpm3 ccp2m2 ccp2m1 ccp2m0 0000 0000 0000 0000 vrcon vren vroen vrr vrss vr3 vr2 vr1 vr0 0000 0000 0000 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 tmr3h timer3 register high byte xxxx xxxx uuuu uuuu tmr3l timer3 register low byte xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu pspcon ibf obf ibov pspmode ?? ? ? 0000 ---- 0000 ---- spbrg usart baud rate generator 0000 0000 0000 0000 rcreg usart receive register 0000 0000 0000 0000 txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren aden ferr oerr rx9d 0000 000x 0000 000x ipr3 irxip wakip errip txb2ip txb1ip txb0ip rxb1ip rxb0ip 1111 1111 1111 1111 pir3 irxif wakif errif txb2if txb1if txb0if rxb1if rxb0if 0000 0000 0000 0000 pie3 irxie wakie errie txb2ie txb1ie txb0ie rxb1ie rxb0ie 0000 0000 0000 0000 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip -1-- 1111 -1-- 1111 pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 trisj (4) data direction control register for portj 1111 1111 1111 1111 trish (4) data direction control register for porth 1111 1111 1111 1111 trisg ? ? ? data direction control register for portg ---1 1111 ---1 1111 trisf data direction control register for portf 1111 1111 1111 1111 trise data direction control register for porte 1111 1111 1111 1111 trisd data direction control register for portd 1111 1111 1111 1111 trisc data direction control register for portc 1111 1111 1111 1111 trisb data direction control register for portb 1111 1111 1111 1111 trisa ? bit 6 (1) data direction control register for porta --11 1111 --11 1111 filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. ? 2000 microchip technology inc. advanced information ds30475a-page 55 pic18cxx8 latj (4) read portj data latch, write portj data latch xxxx xxxx uuuu uuuu lath (4) read porth data latch, write porth data latch xxxx xxxx uuuu uuuu latg ? ? ? read portg data latch, write portg data latch ---x xxxx ---u uuuu latf read portf data latch, write portf data latch xxxx xxxx uuuu uuuu late read porte data latch, write porte data latch xxxx xxxx uuuu uuuu latd read portd data latch, write portd data latch xxxx xxxx uuuu uuuu latc read portc data latch, write portc data latch xxxx xxxx uuuu uuuu latb read portb data latch, write portb data latch xxxx xxxx uuuu uuuu lata ? bit 6 (1) read porta data latch, write porta data latch --xx xxxx --uu uuuu portj (4) read portj pins, write portj data latch xxxx xxxx uuuu uuuu porth (4) read porth pins, write porth data latch xxxx xxxx uuuu uuuu portg ? ? ? read portg pins, write portg data latch ---x xxxx uuuu uuuu portf read portf pins, write portf data latch 0000 0000 0000 0000 porte read porte pins, write porte data latch xxxx xxxx uuuu uuuu portd read portd pins, write portd data latch xxxx xxxx uuuu uuuu portc read portc pins, write portc data latch xxxx xxxx uuuu uuuu portb read portb pins, write portb data latch xxxx xxxx uuuu uuuu porta ? bit 6 (1) read porta pins, write porta data latch --0x 0000 --0u 0000 trisk (4) data direction control register for portk 1111 1111 1111 1111 latk (4) read portk data latch, write portk data latch xxxx xxxx uuuu uuuu portk (4) read portk pins, write portk data latch xxxx xxxx uuuu uuuu txerrcnt tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 0000 0000 0000 0000 rxerrcnt rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 0000 0000 0000 0000 comstat rxb0ovfl rxb1ovfl txbo txbp rxbp txwarn rxwarn ewarn 0000 0000 0000 0000 ciocon tx1src tx1en endrhi cancap ? ? ? ? 1000 ---- 1000 ---- brgcon3 ? wakfil ? ? ? seg2ph2 seg2ph1 seg2ph0 -0-- -000 -0-- -000 brgcon2 seg2phts sam seg1ph2 seg1ph1 seg1ph0 prseg2 prseg1 prseg0 0000 0000 0000 0000 brgcon1 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 0000 0000 0000 0000 cancon reqop2 reqop1 reqop0 abat win2 win1 win0 ? xxxx xxx- uuuu uuu- canstat opmode2 opmode1 opmode0 ? icode2 icode1 icoed0 ? xxx- xxx- uuu- uuu- filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. pic18cxx8 ds30475a-page 56 advanced information ? 2000 microchip technology inc. rxb0d7 rxb0d77 rxb0d76 rxb0d75 rxb0d74 rxb0d73 rxb0d72 rxb0d71 rxb0d70 xxxx xxxx uuuu uuuu rxb0d6 rxb0d67 rxb0d66 rxb0d65 rxb0d64 rxb0d63 rxb0d62 rxb0d61 rxb0d60 xxxx xxxx uuuu uuuu rxb0d5 rxb0d57 rxb0d56 rxb0d55 rxb0d54 rxb0d53 rxb0d52 rxb0d51 rxb0d50 xxxx xxxx uuuu uuuu rxb0d4 rxb0d47 rxb0d46 rxb0d45 rxb0d44 rxb0d43 rxb0d42 rxb0d41 rxb0d40 xxxx xxxx uuuu uuuu rxb0d3 rxb0d37 rxb0d36 rxb0d35 rxb0d34 rxb0d33 rxb0d32 rxb0d31 rxb0d30 xxxx xxxx uuuu uuuu rxb0d2 rxb0d27 rxb0d26 rxb0d25 rxb0d24 rxb0d23 rxb0d22 rxb0d21 rxb0d20 xxxx xxxx uuuu uuuu rxb0d1 rxb0d17 rxb0d16 rxb0d15 rxb0d14 rxb0d13 rxb0d12 rxb0d11 rxb0d10 xxxx xxxx uuuu uuuu rxb0d0 rxb0d07 rxb0d06 rxb0d05 rxb0d04 rxb0d03 rxb0d02 rxb0d0? rxb0d00 xxxx xxxx uuuu uuuu rxb0dlc ? rxrtr resb1 resb0 dlc3 dlc2 dlc1 dlc0 0xxx xxxx 0uuu uuuu rxb0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxb0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxb0sidl sid2 sid1 sid0 srr exid ? eid17 eid16 xxxx x-xx uuuu u-uu rxb0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxb0con rxful rxm1 rxm0 ? rxrtrro rxb0dben jtoff filhit0 000- 0000 000- 0000 canstat opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- uuu- uuu- rxb1d7 rxb1d77 rxb1d76 rxb1d75 rxb1d74 rxb1d73 rxb1d72 rxb1d71 rxb1d70 xxxx xxxx uuuu uuuu rxb1d6 rxb1d67 rxb1d66 rxb1d65 rxb1d64 rxb1d63 rxb1d62 rxb1d61 rxb1d60 xxxx xxxx uuuu uuuu rxb1d5 rxb1d57 rxb1d56 rxb1d55 rxb1d54 rxb1d53 rxb1d52 rxb1d51 rxb1d50 xxxx xxxx uuuu uuuu rxb1d4 rxb1d47 rxb1d46 rxb1d45 rxb1d44 rxb1d43 rxb1d42 rxb1d41 rxb1d40 xxxx xxxx uuuu uuuu rxb1d3 rxb1d37 rxb1d36 rxb1d35 rxb1d34 rxb1d33 rxb1d32 rxb1d31 rxb1d30 xxxx xxxx uuuu uuuu rxb1d2 rxb1d27 rxb1d26 rxb1d25 rxb1d24 rxb1d23 rxb1d22 rxb1d21 rxb1d20 xxxx xxxx uuuu uuuu rxb1d1 rxb1d17 rxb1d16 rxb1d15 rxb1d14 rxb1d13 rxb1d12 rxb1d11 rxb1d10 xxxx xxxx uuuu uuuu rxb1d0 rxb1d07 rxb1d06 rxb1d05 rxb1d04 rxb1d03 rxb1d02 rxb1d01 rxb1d00 xxxx xxxx uuuu uuuu rxb1dlc ? rxrtr resb1 resb0 dlc3 dlc2 dlc1 dlc0 0xxx xxxx 0uuu uuuu rxb1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxb1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxb1sidl sid2 sid1 sid0 srr exid ? eid17 eid16 xxxx x0xx uuuu u0uu rxb1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxb1con rxful rxm1 rxm0 ? rxrtrro filhit2 filhit1 filhit0 0000 0000 0000 0000 canstat opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- uuu- uuu- filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. ? 2000 microchip technology inc. advanced information ds30475a-page 57 pic18cxx8 txb0d7 txb0d77 txb0d76 txb0d75 txb0d74 txb0d73 txb0d72 txb0d71 txb0d70 xxxx xxxx uuuu uuuu txb0d6 txb0d67 txb0d66 txb0d65 txb0d64 txb0d63 txb0d62 txb0d61 txb0d60 xxxx xxxx uuuu uuuu txb0d5 txb0d57 txb0d56 txb0d55 txb0d54 txb0d53 txb0d52 txb0d51 txb0d50 xxxx xxxx uuuu uuuu txb0d4 txb0d47 txb0d46 txb0d45 txb0d44 txb0d43 txb0d42 txb0d41 txb0d40 xxxx xxxx uuuu uuuu txb0d3 txb0d37 txb0d36 txb0d35 txb0d34 txb0d33 txb0d32 txb0d31 txb0d30 xxxx xxxx uuuu uuuu txb0d2 txb0d27 txb0d26 txb0d25 txb0d24 txb0d23 txb0d22 txb0d21 txb0d20 xxxx xxxx uuuu uuuu txb0d1 txb0d17 txb0d16 txb0d15 txb0d14 txb0d13 txb0d12 txb0d11 txb0d10 xxxx xxxx uuuu uuuu txb0d0 txb0d07 txb0d06 txb0d05 txb0d04 txb0d03 txb0d02 txb0d01 txb0d00 xxxx xxxx uuuu uuuu txb0dlc ? txrtr ? ? dlc3 dlc2 dlc1 dlc0 0x00 xxxx 0u00 uuuu txb0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu txb0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu txb0sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx0 x0xx uuu0 u0uu txb0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu txb0con ? txabt txlarb txerr txreq ? txpri1 txpri0 0000 0000 0000 0000 canstat opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- uuu- uuu- txb1d7 txb1d77 txb1d76 txb1d75 txb1d74 txb1d73 txb1d72 txb1d71 txb1d70 xxxx xxxx uuuu uuuu txb1d6 txb1d67 txb1d66 txb1d65 txb1d64 txb1d63 txb1d62 txb1d61 txb1d60 xxxx xxxx uuuu uuuu txb1d5 txb1d57 txb1d56 txb1d55 txb1d54 txb1d53 txb1d52 txb1d51 txb1d50 xxxx xxxx uuuu uuuu txb1d4 txb1d47 txb1d46 txb1d45 txb1d44 txb1d43 txb1d42 txb1d41 txb1d40 xxxx xxxx uuuu uuuu txb1d3 txb1d37 txb1d36 txb1d35 txb1d34 txb1d33 txb1d32 txb1d31 txb1d30 xxxx xxxx uuuu uuuu txb1d2 txb1d27 txb1d26 txb1d25 txb1d24 txb1d23 txb1d22 txb1d21 txb1d20 xxxx xxxx uuuu uuuu txb1d1 txb1d17 txb1d16 txb1d15 txb1d14 txb1d13 txb1d12 txb1d11 txb1d10 xxxx xxxx uuuu uuuu txb1d0 txb1d07 txb1d06 txb1d05 txb1d04 txb1d03 txb1d02 txb1d01 txb1d00 xxxx xxxx uuuu uuuu txb1dlc ? txrtr ? ? dlc3 dlc2 dlc1 dlc0 0x00 xxxx 0u00 uuuu txb1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu txb1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu txb1sidl sid2 sid1 sid0 ? exide ? eid17 eid16 xxx0 x0xx uuu0 u0uu txb1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu txb1con ? txabt txlarb txerr txreq ? txpri1 txpri0 0000 0000 0000 0000 canstat opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? xxx- xxx- uuu- uuu- filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. pic18cxx8 ds30475a-page 58 advanced information ? 2000 microchip technology inc. txb2d7 txb2d77 txb2d76 txb2d75 txb2d74 txb2d73 txb2d72 txb2d71 txb2d70 xxxx xxxx uuuu uuuu txb2d6 txb2d67 txb2d66 txb2d65 txb2d64 txb2d63 txb2d62 txb2d61 txb2d60 xxxx xxxx uuuu uuuu txb2d5 txb2d57 txb2d56 txb2d55 txb2d54 txb2d53 txb2d52 txb2d51 txb2d50 xxxx xxxx uuuu uuuu txb2d4 txb2d47 txb2d46 txb2d45 txb2d44 txb2d43 txb2d42 txb2d41 txb2d40 xxxx xxxx uuuu uuuu txb2d3 txb2d37 txb2d36 txb2d35 txb2d34 txb2d33 txb2d32 txb2d31 txb2d30 xxxx xxxx uuuu uuuu txb2d2 txb2d27 txb2d26 txb2d25 txb2d24 txb2d23 txb2d22 txb2d21 txb2d20 xxxx xxxx uuuu uuuu txb2d1 txb2d17 txb2d16 txb2d15 txb2d14 txb2d13 txb2d12 txb2d11 txb2d10 xxxx xxxx uuuu uuuu txb2d0 txb2d07 txb2d06 txb2d05 txb2d04 txb2d03 txb2d02 txb2d01 txb2d00 xxxx xxxx uuuu uuuu txb2dlc ? txrtr ? ? dlc3 dlc2 dlc1 dlc0 0x00 xxxx 0u00 uuuu txb2eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu txb2eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu txb2sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx0 x0xx uuu0 u0uu txb2sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu txb2con ? txabt txlarb txerr txreq ? txpri1 txpri0 0000 0000 0000 0000 rxm1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxm1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxm1sidl sid2 sid1 sid0 ? ? ? eid17 eid16 xxx- --xx uuu- --uu rxm1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxm0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxm0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxm0sidl sid2 sid1 sid0 ? ? ? eid17 eid16 xxx- --xx uuu- --uu rxm0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxf5eid0 eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxf5eid8 eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxf5sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx- x-xx uuu- u-uu rxf5sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxf4eid0 eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxf4eid8 eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxf4sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx- x-xx uuu- u-uu rxf4sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxf3eid0 eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxf3eid8 eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxf3sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx- x-xx uuu- u-uu rxf3sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. ? 2000 microchip technology inc. advanced information ds30475a-page 59 pic18cxx8 rxf2eid0 eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxf2eid8 eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxf2sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx- x-xx uuu- u-uu rxf2sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxf1eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxf1eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxf1sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx- x-xx uuu- u-uu rxf1sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu rxf0eidl eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 xxxx xxxx uuuu uuuu rxf0eidh eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 xxxx xxxx uuuu uuuu rxf0sidl sid2 sid1 sid0 ? exiden ? eid17 eid16 xxx- x-xx uuu- u-uu rxf0sidh sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 xxxx xxxx uuuu uuuu filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (3) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disa bled and read ? 0 ? . 2: bit 21 of the tblptru allows access to the device configuration bits. 3: other (non-power-up) resets include external reset through mclr and watchdog timer reset. 4: these registers are reserved on pic18c658. pic18cxx8 ds30475a-page 60 advanced information ? 2000 microchip technology inc. 4.10 a ccess bank the access bank is an architectural enhancement that is very useful for c compiler code optimization. the techniques used by the c compiler are also be useful for programs written in assembly. this data memory region can be used for: intermediate computational values local variables of subroutines faster context saving/switching of variables common variables faster evaluation/control of sfr ? s (no banking) the access bank is comprised of the upper 160 bytes in bank 15 (sfr ? s) and the lower 96 bytes in bank 0. these two sections will be referred to as access bank high and access bank low, respectively. figure 4-4 indicates the access bank areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register, or in the access bank. when forced in the access bank (a = ? 0 ? ), the last address in access bank low is followed by the first address in access bank high. access bank high maps most of the special function registers so that these registers can be accessed without any software over- head. 4.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ? 0 ? s, and writes will have no effect. a movlb instruction has been provided in the instruc- tion set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr, since the 12-bit addresses are embedded into the instruction word. section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire ram space. figure 4-5: direct addressing note 1: for register file map detail, see table 4-2. 2: the access bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory ( 1 ) direct addressing bank select ( 2 ) location select ( 3 ) bsr<3:0> 7 0 from opcode ( 3 ) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h ? 2000 microchip technology inc. advanced information ds30475a-page 61 pic18cxx8 4.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. a sfr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be mod- ified by the program. this can be useful for data tables in the data memory and for software stacks. figure 4-6 shows the operation of indirect addressing. this shows the moving of the value to the data memory address specified by the value of the fsr register. indirect addressing is possible by using one of the indf registers. any instruction using the indf register actually accesses the register indicated by the file select register, fsr. reading the indf register itself indirectly (fsr = ? 0 ? ) will read 00h. writing to the indf register indirectly results in a no-operation. the fsr register contains a 12-bit address, which is shown in figure 4-6. the indfn (0 n 2) register is not a physical register. addressing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer). this is indirect addressing. example 4-4 shows a simple use of indirect addressing to clear the ram in bank 1 (locations 100h-1ffh) in a minimum number of instructions. example 4-4: how to clear ram (bank 1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12-bit wide. to store the 12-bits of addressing information, two 8-bit registers are required. these indirect addressing registers are: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing, with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address indicated by fsr0h:fsr0l. a read from indf1 reads the data from the address indicated by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1 or indf2 are read indirectly via an fsr, all ? 0 ? s are read (zero bit is set). similarly, if indf0, indf1 or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 4.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. performing an operation on one of these five registers determines how the fsr will be modified during indirect addressing. when data access is done to one of the five indfn locations, the address selected will configure the fsrn register to: do nothing to fsrn after an indirect access (no change) - indfn auto-decrement fsrn after an indirect access (post-decrement) - postdecn auto-increment fsrn after an indirect access (post-increment) - postincn auto-increment fsrn before an indirect access (pre-increment) - preincn use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) - pluswn when using the auto-increment or auto-decrement features, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal '0', the z bit will not be set. incrementing or decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a software stack pointer in addition to its uses for table operations in data memory. each fsr has an address associated with it that per- forms an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the 2 ? s complement value in the wreg register and the value in fsr to form the address before an indirect access. the fsr value is not changed. if an fsr register contains a value that indicates one of the indfn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a nop (status bits are not affected). if an indirect addressing operation is done where the target address is an fsrnh or fsrnl register, the write operation will dominate over the pre- or post-increment/decrement functions. lfsr fsr0, 0x100 ; next clrf postinc0 ; c lear indf ; register ; & inc pointer btfss fsr0h, 1 ; all done ; w/ bank1? goto next ; no, clear next continue ; : ; yes, continue pic18cxx8 ds30475a-page 62 advanced information ? 2000 microchip technology inc. figure 4-6: indirect addressing note 1: for register file map detail, see table 4-2. data memory ( 1 ) indirect addressing fsr register 11 8 7 0 0fffh 0000h location select fsrnh fsrnl ? 2000 microchip technology inc. advanced information ds30475a-page 63 pic18cxx8 4.13 status register the status register, shown in register 4-2, contains the arithmetic status of the alu. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. there- fore, the result of an instruction with the status regis- ter as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register, because these instruc- tions do not affect the z, c, dc, ov or n bits from the status register. for other instructions which do not affect the status bits, see table 23-2. register 4-2: status register note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as '0' bit 4 n: negative bit this bit is used for signed arithmetic (2 ? s complement). it indicates whether the result of the alu operation was negative, (alu msb = 1) 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2 ? s complement). it indicates an overflow of the 7-bit mag- nitude, which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf, addlw, sublw, and subwf instructions 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrcf, rrncf, rlcf, and rlncf ) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf, addlw, sublw, and subwf instructions 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the two ? s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 64 advanced information ? 2000 microchip technology inc. 4.13.1 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. register 4-3: rcon register note 1: if the boren configuration bit is set, bor is ? 1 ? on power-on reset. if the boren configuration bit is clear, bor is unknown on power-on reset. the bor status bit is a ? don't care ? and is not necessarily predictable if the brown-out circuit is disabled (the boren configuration bit is clear). bor must then be set by the user and checked on subse- quent resets to see if it is clear, indicat- ing a brown-out has occurred. 2: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen lwrt ? ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 lwrt: long write enable bit 1 = enable tblwt to internal program memory once this bit is set, it can only be cleared by a por or mclr reset 0 = disable tblwt to internal program memory; tblwt only to external program memory bit 5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 65 pic18cxx8 5.0 table reads/table writes all picmicro ? devices have two memory spaces: the program memory space and the data memory space. table reads and table writes have been provided to move data between these two memory spaces through an 8-bit register (tablat). the operations that allow the processor to move data between the data and program memory spaces are: table read ( tblrd ) table write ( tblwt ) table read operations retrieve data from program memory and place it into the data memory space. figure 5-1 shows the operation of a table read with program and data memory. table write operations store data from the data mem- ory space into program memory. figure 5-2 shows the operation of a table write with program and data memory. table operations work with byte entities. a table block containing data is not required to be word aligned, so a table block can start and end at any byte address. if a table write is being used to write an executable pro- gram to program memory, program instructions will need to be word aligned. figure 5-1: table read operation figure 5-2: table write operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer points to a byte in program memory. program memory (tblptr) table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer points to a byte in program memory. pic18cxx8 ds30475a-page 66 advanced information ? 2000 microchip technology inc. 5.1 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include: rcon register tablat register tblptr registers 5.1.1 rcon register the lwrt bit specifies the operation of table writes to internal memory when the v pp voltage is applied to the mclr pin. when the lwrt bit is set, the controller continues to execute user code, but long table writes are allowed (for programming internal program mem- ory) from user mode. the lwrt bit can be cleared only by performing either a por or mclr reset. register 5-1: rcon register (address: 0xfd0h) r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen lwrt ? ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 lwrt: long write enable 1 = enable tblwt to internal program memory 0 = disable tblwt to internal program memory. note 1: only cleared on a por or mclr reset. this bit has no effect on tblwts to external program memory. bit 5 unimplemented : read as '0' bit 4 ri : reset instruction flag bit 1 = no reset instruction occurred 0 = a reset instruction occurred bit 3 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset nor por reset occurred 0 = a brown-out reset or por reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 67 pic18cxx8 5.1.2 tablat - table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch is used to hold 8-bit data during data transfers between program memory and data memory. 5.1.3 tblptr - table pointer register the table pointer (tblptr) addresses a byte within the program memory. the tblptr is comprised of three sfr registers (table pointer upper byte, high byte and low byte). these three registers (tblptru:tblptrh:tblptrl) join to form a 22-bit wide pointer. the low order 21-bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows read only access to the device id, the user id and the configuration bits. the table pointer tblptr is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table oper- ation. these operations are shown in table 5-1. these operations on the tblptr only affect the low order 21-bits. table 5-1: table pointer operations with tblrd and tblwt instructions example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write pic18cxx8 ds30475a-page 68 advanced information ? 2000 microchip technology inc. 5.2 p rogram memory read/writes 5.2.1 table read overview (tblrd) the tblrd instructions are used to read data from pro- gram memory to data memory. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified auto- matically for the next table read operation. table reads from program memory are performed one byte at a time. the instruction will load tablat with the one byte from program memory pointed to by tblptr. 5.2.2 program memory write block size the program memory of pic18cxx8 devices is written in blocks. for pic18cxx8 devices, the write block size is 2 bytes. consequently, table write operations to program memory are performed in pairs, one byte at a time. when a table write occurs to an even program mem- ory address (tblptr<0> = 0), the contents of tablat are transferred to an internal holding register. this is performed as a short write and the program memory block is not actually programmed at this time. the holding register is not accessible by the user. when a table write occurs to an odd program memory address (tblptr<0> = 1), a long write is started. dur- ing the long write, the contents of tablat are written to the high byte of the program memory block and the contents of the holding register are transferred to the low byte of the program memory block. figure 5-3 shows the holding register and the program memory write blocks. if a single byte is to be programmed, the low (even) byte of the destination program word should be read using tblrd *, modified or changed, if required, and written back to the same address using tblwt*+ . the high (odd) byte should be read using tblrd* , modified or changed if required, and written back to the same address using tblwt . the write to an odd address will cause a long write to begin. this process ensures that existing data in either byte will not be changed unless desired. figure 5-3: holding register and the write example 5-1: table read code example ; read a byte from location 0x0020 clrf tblptru ; load upper 5 bits of ; 0x0020 clrf tblptrh ; load higher 8 bits of ; 0x0020 movlw 0x20 ; load 0x20 into movwf tblptrl ; tblptrl movwf tblrd* ; data is in tablat program memory holding register instruction execution ; tablptr points to address n movlw datalow ; load low data msb lsb movwf tablat ; byte to tablat datalow tblwt*+ ; write it to lsb ; of holding register movlw datahigh ; load high data n - 1 msb lsb movwf tablat ; byte to tablat n datalow datahigh datalow tblwt* ; write it to msb n + 1 datahigh ; of holding n + 2 ; register and ; begin long ; write ? 2000 microchip technology inc. advanced information ds30475a-page 69 pic18cxx8 5.2.2.1 long write operation the long write is what actually programs words of data into the internal memory. when a tblwt to the msb of the write block occurs, instruction execution is halted. during this time, programming voltage and the data stored in internal latches is applied to program memory. for a long write to occur: 1. mclr /v pp pin must be at the programming voltage 2. lwrt bit must be set 3. tblwt to the address of the msb of the write block if the lwrt bit is clear, a short write will occur and pro- gram memory will not be changed. if the tblwt is not to the msb of the write block, then the programming phase is not initiated. setting the lwrt bit enables long writes when the mclr pin is taken to v pp voltage. once the lwrt bit is set, it can be cleared only by performing a por or mclr reset. to ensure that the memory location has been well pro- grammed, a minimum programming time is required. the long write can be terminated after the program- ming time has expired by a reset or an interrupt. having only one interrupt source enabled to terminate the long write, ensures that no unintended interrupts will prematurely terminate the long write. 5.2.2.2 sequence of events the sequence of events for programming an internal program memory location should be: 1. enable the interrupt that terminates the long write. disable all other interrupts. 2. clear the source interrupt flag. 3. if interrupt service routine execution is desired when the device wakes, enable global interrupts. 4. set lwrt bit in the rcon register. 5. raise mclr /v pp pin to the programming voltage, v pp . 6. clear the wdt (if enabled). 7. set the interrupt source to interrupt at the required time. 8. execute the table write for the lower (even) byte. this will be a short write. 9. execute the table write for the upper (odd) byte. this will be a long write. the controller will halt while programming. the interrupt wakes the controller. 10. if gie was set, service the interrupt request. 11. go to 7 if more bytes to be programmed. 12. lower mclr /v pp pin to v dd . 13. verify the memory location (table read). 14. reset the device. pic18cxx8 ds30475a-page 70 advanced information ? 2000 microchip technology inc. 5.2.3 long write interrupts the long write must be terminated by a reset or any interrupt. the interrupt source must have its interrupt enable bit set. when the source sets its interrupt flag, program- ming will terminate. this will occur regardless of the settings of interrupt priority bits, the gie/gieh bit or the pie/giel bit. depending on the states of interrupt priority bits, the gie/gieh bit or the pie/giel bit, program execution can either be vectored to the high or low priority inter- rupt service routine (isr), or continue execution from where programming commenced. in either case, the interrupt flag will not be cleared when programming is terminated and will need to be cleared by the software. 5.3 unexpected termination of write operations if a write is terminated by an unplanned event such as loss of power, an unexpected reset, or an interrupt that was not disabled, the memory location just pro- grammed should be verified and reprogrammed if needed. table 5-2: sleep mode, interrupt enable bits and interrupt results gie/ gieh pie/ giel priority interrupt enable interrupt flag action xx x 0 (default) x long write continues even if interrupt flag becomes set during sleep. x x x 1 0 long write continues, will wake when the interrupt flag is set. 0 (default) 0 (default) x 1 1 terminates long write, executes next instruction. interrupt flag not cleared. 0 (default) 11 high priority (default) 1 1 terminates long write, executes next instruction. interrupt flag not cleared. 10 (default) 0 low 1 1 terminates long write, executes next instruction. interrupt flag not cleared. 0 (default) 10 low 1 1 terminates long write, branches to low priority interrupt vector. interrupt flag can be cleared by isr. 10 (default) 1 high priority (default) 1 1 terminates long write, branches to high priority interrupt vector. interrupt flag can be cleared by isr. ? 2000 microchip technology inc. advanced information ds30475a-page 71 pic18cxx8 6.0 8 x 8 hardware multiplier an 8 x 8 hardware multiplier is included in the alu of the pic18cxx8 devices. by making the multiply a hardware operation, it completes in a single instruction cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product regis- ter pair (prodh:prodl). the multiplier does not affect any flags in the status register. making the 8 x 8 multiplier execute in a single cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algo- rithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 6-1 shows a performance comparison between enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply. table 6-1: performance comparison routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s27.6 s69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s36.4 s91 s hardware multiply 6 6 600 ns 2.4 s 6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s96.8 s 242 s hardware multiply 24 24 2.4 s 9.6 s 24 s 16 x 16 signed without hardware multiply 52 254 25.4 s102.6 s 254 s hardware multiply 36 36 3.6 s 14.4 s 36 s pic18cxx8 ds30475a-page 72 advanced information ? 2000 microchip technology inc. 6.1 operation example 6-1 shows the sequence to perform an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 6-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each argument ? s most significant bit (msb) is tested and the appropriate subtractions are done. example 6-1: 8 x 8 unsigned multiply routine example 6-2: 8 x 8 signed multiply routine example 6-3 shows the sequence to perform a 16 x 16 unsigned multiply. equation 6-1 shows the algorithm that is used. the 32-bit result is stored in 4 registers res3:res0. equation 6-1: 16 x 16 unsigned multiplication algorithm example 6-3: 16 x 16 unsigned multiply routine movff arg1, wreg ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movff arg1, wreg mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movff arg2, wreg btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l) movff arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movff arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movff arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movff arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ? 2000 microchip technology inc. advanced information ds30475a-page 73 pic18cxx8 example 6-4 shows the sequence to perform an 16 x 16 signed multiply. equation 6-2 shows the algorithm used. the 32-bit result is stored in four registers res3:res0. to account for the sign bits of the argu- ments, each argument pairs most significant bit (msb) is tested and the appropriate subtractions are done. equation 6-2: 16 x 16 signed multiplication algorithm example 6-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 )+ (arg1h ? arg2l ? 2 8 )+ (arg1l ? arg2h ? 2 8 )+ (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 )+ (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movff arg1l, wreg mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movff arg1h, wreg mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movff arg1l, wreg mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movff arg1h, wreg ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? goto sign_arg1 ; no, check arg1 movff arg1l, wreg ; subwf res2 ; movff arg1h, wreg ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? goto cont_code ; no, done movff arg2l, wreg ; subwf res2 ; movff arg2h, wreg ; subwfb res3 ; cont_code : pic18cxx8 ds30475a-page 74 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 75 pic18cxx8 7.0 interrupts the pic18cxx8 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will over- ride any low priority interrupts that may be in progress. there are 13 registers that are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2, pir3 pie1, pie2, pie3 ipr1, ipr2, ipr3 it is recommended that the microchip header files sup- plied with mplab be used for the symbolic bit names in these registers. this allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. each interrupt source has three bits to control its oper- ation. the functions of these bits are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon register). when interrupt priority is enabled, there are two bits that enable interrupts glo- bally. setting the gieh bit (intcon register) enables all interrupts that have the priority bit set. setting the giel bit (intcon register) enables all interrupts that have the priority bit cleared. when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. individual interrupts can be disabled through their cor- responding enable bits. when the ipen bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are com- patible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. the peie bit (intcon register) enables/disables all peripheral interrupt sources. the gie bit (intcon register) enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt prior- ity levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the "return from interrupt" instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the gie bit. pic18cxx8 ds30475a-page 76 advanced information ? 2000 microchip technology inc. figure 7-1: interrupt logic tmr0ie gie/gieh giel/peie wake-up if in sleep mode interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip int0if int0ie rbif rbie rbip tmr0if tmr0ip int1if int1ie int1 i p int2if int2ie int2 i p rbif rbie rbip int0if int0ie peie/giel interrupt to cpu vector to location ipen 0018h peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit peripheral interrupt flag bit peripheral interrupt enable bit peripheral interrupt priority bit tmr1if tmr1ie tmr1ip xxxxif xxxxie xxxxip additional peripheral interrupts tmr1if tmr1ie tmr1ip high priority interrupt generation low priority interrupt generation xxxxif xxxxie xxxxip additional peripheral interrupts ipen ipen int3if int3ie int 3ip int3if int3ie int 3ip ? 2000 microchip technology inc. advanced information ds30475a-page 77 pic18cxx8 7.1 control registers this section contains the control and status registers. 7.1.1 intcon registers the intcon registers are readable and writable registers, which contain various enable, priority, and flag bits. register 7-1: intcon register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit w hen ipen = 0 : 1 = enables all un-masked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all high priority interrupts bit 6 peie/giel: peripheral interrupt enable bit w hen ipen = 0 : 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software by reading portb) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling. pic18cxx8 ds30475a-page 78 advanced information ? 2000 microchip technology inc. register 7-2: intcon2 register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0 : external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1 : external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2 : external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3: external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip : tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 int3ip : int3 external interrupt priority bit 1 = high priority 0 = low priority bit 0 rbip : rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling. ? 2000 microchip technology inc. advanced information ds30475a-page 79 pic18cxx8 register 7-3: intcon3 register r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: i nt3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows software polling. pic18cxx8 ds30475a-page 80 advanced information ? 2000 microchip technology inc. 7.1.2 pir registers the peripheral interrupt request (pir) registers con- tain the individual flag bits for the peripheral interrupts (register 7-5). due to the number of peripheral inter- rupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). 7.1.3 pie registers the peripheral interrupt enable (pie) registers contain the individual enable bits for the peripheral interrupts (register 7-5). due to the number of peripheral inter- rupt sources, there are three peripheral interrupt enable registers (pie1, pie2, pie3). when ipen is clear, the peie bit must be set to enable any of these peripheral interrupts. 7.1.4 ipr registers the interrupt priority (ipr) registers contain the individ- ual priority bits for the peripheral interrupts (register 7-7). due to the number of peripheral inter- rupt sources, there are three peripheral interrupt prior- ity registers (ipr1, ipr2, ipr3). the operation of the priority bits requires that the interrupt priority enable bit (ipen) be set. 7.1.5 rcon register the reset control (rcon) register contains the bit that is used to enable prioritized interrupts (ipen). register 7-4: rcon register note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon register). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 ipen lwrt ? ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (16cxxx compatibility mode) bit 6 lwrt: long write enable for details of bit operation see register 4-3 bit 5 unimplemented: read as '0' bit 4 ri : reset instruction flag bit for details of bit operation see register 4-3 bit 3 to : watchdog time-out flag bit for details of bit operation see register 4-3 bit 2 pd : power-down detection flag bit for details of bit operation see register 4-3 bit 1 por : power-on reset status bit for details of bit operation see register 4-3 bit 0 bor : brown-out reset status bit for details of bit operation see register 4-3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 81 pic18cxx8 register 7-5: pir registers r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if bit 7 bit 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pir3 irxif wakif errif txb2if txb1if txb0if rxb1if rxb0if bit 7 bit 0 pir1 bit 7 pspif: parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif : a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif : usart receive interrupt flag bit 1 = the usart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the usart receive buffer is empty bit 4 txif : usart transmit interrupt flag bit 1 = the usart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the usart transmit buffer is full bit 3 sspif : master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if : ccp1 interrupt flag bit capture mode 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow pic18cxx8 ds30475a-page 82 advanced information ? 2000 microchip technology inc. register 7-5: pir registers (cont ? d) pir2 bit 7 unimplemented: read as ? 0 ? bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed 0 = comparator input has not changed bit 5-4 unimplemented: read as ? 0 ? bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif: low voltage detect interrupt flag bit 1 = a low voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if: ccpx interrupt flag bit capture mod e 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode unused in this mode ? 2000 microchip technology inc. advanced information ds30475a-page 83 pic18cxx8 register 7-5: pir registers (cont ? d) pir3 bit 7 irxif: invalid message received interrupt flag bit 1 = an invalid message has occurred on the can bus 0 = an invalid message has not occurred on the can bus bit 6 wakif: bus activity wake-up interrupt flag bit 1 = activity on the can bus has occurred 0 = activity on the can bus has not occurred bit 5 errif: can bus error interrupt flag bit 1 = an error has occurred in the can module (multiple sources) 0 = an error has not occurred in the can module bit 4 txb2if: transmit buffer 2 interrupt flag bit 1 = transmit buffer 2 has completed transmission of a message, and may be reloaded 0 = transmit buffer 2 has not completed transmission of a message bit 3 txb1if: transmit buffer 1 interrupt flag bit 1 = transmit buffer 1 has completed transmission of a message, and may be reloaded 0 = transmit buffer 1 has not completed transmission of a message bit 2 txb0if: transmit buffer 0 interrupt flag bit 1 = transmit buffer 0 has completed transmission of a message, and may be reloaded 0 = transmit buffer 0 has not completed transmission of a message bit 1 rxb1if: receive buffer 1 interrupt flag bit 1 = receive buffer 1 has received a new message 0 = receive buffer 1 has not received a new message bit 0 rxb0if: receive buffer 0 interrupt flag bit 1 = receive buffer 0 has received a new message 0 = receive buffer 0 has not received a new message legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 84 advanced information ? 2000 microchip technology inc. register 7-6: pie registers r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie bit 7 bit 0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pie3 ivre wakie errie txb2ie txb1ie txb0ie rxb1ie rxb0ie bit 7 bit 0 pie1 bit 7 pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie : a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie : usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie : usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie : master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie : ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie : tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie : tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt ? 2000 microchip technology inc. advanced information ds30475a-page 85 pic18cxx8 register 7-6: pie registers (cont ? d) pie2 bit 7 unimplemented: read as ? 0 ? bit 6 cmie: comparator interrupt enable bit 1 = enables the comparator interrupt 0 = disables the comparator interrupt bit 5-4 unimplemented: read as ? 0 ? bit 3 bclie : bus collision interrupt enable bit 1 = enabled 0 = disabled bit 2 lvdie : low-voltage detect interrupt enable bit 1 = enabled 0 = disabled bit 1 tmr3ie : tmr3 overflow interrupt enable bit 1 = enables the tmr3 overflow interrupt 0 = disables the tmr3 overflow interrupt bit 0 ccp2ie : ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt pie3 bit 7 ivre: invalid can message received interrupt enable bit 1 = enables the invalid can message received interrupt 0 = disables the invalid can message received interrupt bit 6 wakie: bus activity wake-up interrupt enable bit 1 = enables the bus activity wake-up interrupt 0 = disables the bus activity wake-up interrupt bit 5 errie: can bus error interrupt enable bit 1 = enables the can bus error interrupt 0 = disables the can bus error interrupt bit 4 txb2ie: transmit buffer 2 interrupt enable bit 1 = enables the transmit buffer 2 interrupt 0 = disables the transmit buffer 2 interrupt bit 3 txb1ie: transmit buffer 1 interrupt enable bit 1 = enables the transmit buffer 1 interrupt 0 = disables the transmit buffer 1 interrupt bit 2 txb0ie: transmit buffer 0 interrupt enable bit 1 = enables the transmit buffer 0 interrupt 0 = disables the transmit buffer 0 interrupt bit 1 rxb1ie: receive buffer 1 interrupt enable bit 1 = enables the receive buffer 1 interrupt 0 = disables the receive buffer 1 interrupt bit 0 rxb0ie: receive buffer 0 interrupt enable bit 1 = enables the receive buffer 0 interrupt 0 = disables the receive buffer 0 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 86 advanced information ? 2000 microchip technology inc. register 7-7: ipr registers r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 u-0 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip bit 7 bit 0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ipr3 ivrp wakip errip txb2ip txb1ip txb0ip rxb1ip rxb0ip bit 7 bit 0 ipr1 bit 7 pspip: parallel slave port read/write interrupt priority bit 1 = high priority 0 = low priority bit 6 adip : a/d converter interrupt priority bit 1 = high priority 0 = low priority bit 5 rcip : usart receive interrupt priority bit 1 = high priority 0 = low priority bit 4 txip : usart transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 sspip : master synchronous serial port interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp1ip : ccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip : tmr2 to pr2 match interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1ip : tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority ? 2000 microchip technology inc. advanced information ds30475a-page 87 pic18cxx8 register 7-7: ipr registers (cont ? d) ipr2 bit 7 unimplemented: read as ? 0 ? bit 6 cmip: comparator interrupt priority bit 1 = high priority 0 = low priority bit 5-4 unimplemented: read as ? 0 ? bit 3 bclip : bus collision interrupt priority bit 1 = high priority 0 = low priority bit 2 lvdip : low voltage detect interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr3ip : tmr3 overflow interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp2ip : ccp2 interrupt priority bit 1 = high priority 0 = low priority ipr3 bit 7 ivrp: invalid message received interrupt priority bit 1 = high priority 0 = low priority bit 6 wakip: bus activity wake-up interrupt priority bit 1 = high priority 0 = low priority bit 5 errip: can bus error interrupt priority bit 1 = high priority 0 = low priority bit 4 txb2ip: transmit buffer 2 interrupt priority bit 1 = high priority 0 = low priority bit 3 txb1ip: transmit buffer 1 interrupt priority bit 1 = high priority 0 = low priority bit 2 txb0ip: transmit buffer 0 interrupt priority bit 1 = high priority 0 = low priority bit 1 rxb1ip: receive buffer 1 interrupt priority bit 1 = high priority 0 = low priority bit 0 rxb0ip: receive buffer 0 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 88 advanced information ? 2000 microchip technology inc. 7.1.6 int interrupts external interrupts on the rb0/int0, rb1/int1, rb2/int2, and rb3/int3 pins are edge triggered: either rising if the corresponding intedgx bit is set in the intcon2 register, or falling, if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit intxif is set. this interrupt can be disabled by clearing the corresponding enable bit intxie. flag bit intxif must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1, int2, and int3) can wake-up the processor from sleep, if bit intxie was set prior to going into sleep. if the global interrupt enable bit gie is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits int1ip (intcon3 register), int3ip (intcon3 regis- ter), and int2ip (intcon2 register). there is no prior- ity bit associated with int0; it is always a high priority interrupt source. 7.1.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if. in 16-bit mode, an overflow (ffffh 0000h) in the tmr0h:tmr0l registers will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit tmr0ie (intcon register). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit tmr0ip (intcon2 register). see section 10.0 for further details on the timer0 module. 7.1.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit rbif (intcon register). the interrupt can be enabled/ disabled by setting/clearing enable bit rbie (intcon register). interrupt priority for portb interrupt- on-change is determined by the value contained in the interrupt priority bit rbip (intcon2 register). 7.2 context saving during interrupts during an interrupt, the return pc value is saved on the stack. additionally, the wreg, status and bsr reg- isters are saved on the fast return stack. if a fast return from interrupt is not used (see section 4.3), the user may need to save the wreg, status and bsr regis- ters in software. depending on the user ? s application, other registers may also need to be saved. example 7-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 7-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in low access bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status ? 2000 microchip technology inc. advanced information ds30475a-page 89 pic18cxx8 8.0 i/o ports depending on the device selected, there are up to eleven ports available. some pins of the i/o ports are multiplexed with an alternate function from the periph- eral features on the device. in general, when a periph- eral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch) the data latch (lat register) is useful for read-modify-write operations on the value that the i/o pins are driving. 8.1 porta, trisa and lata registers porta is a 6-bit wide, bi-directional port. the corre- sponding data direction register is trisa. setting a trisa bit (=1) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisa bit (=0) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). on a power-on reset, these pins are configured as inputs and read as '0'. reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. read-modify-write operations on the lata register, reads and writes the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the ra4/t0cki pin is a schmitt trigger input and an open drain output. all other ra port pins have ttl input lev- els and full cmos output drivers. the other porta pins are multiplexed with analog inputs and the analog v ref + and v ref - inputs. the operation of each pin is selected by clearing/setting the control bits in the adcon1 register (a/d control register1). on a power-on reset, these pins are con- figured as analog inputs and read as '0'. the trisa register controls the direction of the ra pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 8-1: initializing porta figure 8-1: ra3:ra0 and ra5 pins block diagram clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 0x07 ; configure a/d movwf adcon1 ; for digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra3:ra0 as inputs ; ra5:ra4 as outputs data bus q d q ck q d q ck qd en p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . analog input mode ttl input buffer to a/d converter and lvd modules rd lata or wr porta ss input (ra5 only) pic18cxx8 ds30475a-page 90 advanced information ? 2000 microchip technology inc. figure 8-2: ra4/t0cki pin block diagram figure 8-3: ra6 block diagram table 8-1: porta functions table 8-2: summary of registers associated with porta data bus wr trisa rd porta data latch tris latch rd trisa schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input note 1: i/o pin has diode protection to v ss only. q d q ck q d q ck en qd en rd lata wr lata or wr porta data bus q d q ck qd en p n wr lata wr data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . or wr porta rd lata ecra6 or data bus ecra6 or enable data bus ttl input buffer rcra6 rcra6 enable trisa q d q ck name bit# buffer function ra0/an0 bit0 ttl input/output or analog input. ra1/an1 bit1 ttl input/output or analog input. ra2/an2/v ref - bit2 ttl input/output or analog input or v ref -. ra3/an3/v ref + bit3 ttl input/output or analog input or v ref +. ra4/t0cki bit4 st/od input/output or external clock input for timer0 output is open drain type. ra5/ss/ an4/lvdin bit5 ttl input/output or slave select input for synchronous serial port or analog input, or low voltage detect input. osc2/clko/ra6 bit6 ttl osc2 or clock output or i/o pin. legend: ttl = ttl input, st = schmitt trigger input, od = open drain name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ? ra6 ra5 ra4 ra3 ra2 ra1 ra0 -x0x 0000 -uuu uuuu lata ? latch a data output register -xxx xxxx -uuu uuuu trisa ? porta data direction register -111 1111 -111 1111 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --uu uuuu legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by porta. ? 2000 microchip technology inc. advanced information ds30475a-page 91 pic18cxx8 8.2 p ortb, trisb and latb registers portb is an 8-bit wide bi-directional port. the corre- sponding data direction register is trisb. setting a trisb bit (=1) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisb bit (=0) will make the corresponding portb pin an output ( i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latb register read and write the latched output value for portb. example 8-2: initializing portb figure 8-4: rb7:rb4 pins block diagram each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (intcon2 register). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset. four of portb ? s pins, rb7:rb4, have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ? mismatch ? outputs of rb7:rb4 are or ? d together to generate the rb port change interrupt with flag bit rbif (intcon register). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt-on-change feature. figure 8-5: rb3:rb0 pins block diagram clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb3:rb0 as inputs ; rb5:rb4 as outputs ; rb7:rb6 as inputs data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb4 pins weak pull-up rd portb latch ttl input buffer st buffer rbx/intx q3 q1 rd latb or wr portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2 register). data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rbx/intx i/o pin (1) ttl input buffer schmitt trigger buffer tris latch note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2 register). pic18cxx8 ds30475a-page 92 advanced information ? 2000 microchip technology inc. table 8-3: portb functions table 8-4: summary of registers associated with portb name bit# buffer function rb0/int0 bit0 ttl/st (1) input/output pin or external interrupt 0 input. internal software programmable weak pull-up. rb1/int1 bit1 ttl/st (1) input/output pin or external interrupt 1 input. internal software programmable weak pull-up. rb2/int2 bit2 ttl/st (1) input/output pin or external interrupt 2 input. internal software programmable weak pull-up. rb3/int3 bit3 ttl/st (1) input/output pin or external interrupt 3 input. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt-on-change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7 bit7 ttl/st (2) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a schmitt trigger input when configured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu latb latb data output register xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 1111 1111 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 1100 0000 legend: x = unknown, u = unchanged. shaded cells are not used by portb. ? 2000 microchip technology inc. advanced information ds30475a-page 93 pic18cxx8 8.3 portc, trisc and latc registers portc is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisc. setting a trisc bit (=1) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisc bit (=0) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latc register, read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 8-5). portc pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an out- put, while other peripherals override the tris bit to make a pin an input. the user should refer to the correspond- ing peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris reg- ister. this allows read-modify-write of the tris register, without concern due to peripheral overrides. example 8-3: initializing portc figure 8-6: portc block diagram (peripheral output override) clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc3:rc0 as inputs ; rc5:rc4 as outputs ; rc7:rc6 as inputs peripheral out select data bus wr latc wr trisc data latch tris latch rd trisc q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd portc peripheral data in i/o pin or wr portc rd latc schmitt trigger note: i/o pins have diode protection to v dd and v ss . tris override peripheral enable tris override pin override peripheral rc0 yes timer1 osc for timer1/timer3 rc1 yes timer1 osc for timer1/timer3 rc2 no ? rc3 yes spi/i 2 c master clock rc4 yes i 2 c data out rc5 yes spi data out rc6 yes usart async xmit, sync clock rc7 yes usart sync data out pic18cxx8 ds30475a-page 94 advanced information ? 2000 microchip technology inc. table 8-5: portc functions table 8-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t13cki bit0 st input/output port pin or timer1 oscillator output or timer1/timer3 clock input. rc1/t1osi bit1 st input/output port pin or timer1 oscillator input. rc2/ccp1 bit2 st input/output port pin or capture1 input/compare1 output/pwm1 output. rc3/sck/scl bit3 st input/output port pin or synchronous serial clock for spi/i 2 c. rc4/sdi/sda bit4 st input/output port pin or spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit6 st input/output port pin addressable usart asynchronous transmit or addressable usart synchronous clock. rc7/rx/dt bit7 st input/output port pin addressable usart asynchronous receive or addressable usart synchronous data. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu latc latc data output register xxxx xxxx uuuu uuuu trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged ? 2000 microchip technology inc. advanced information ds30475a-page 95 pic18cxx8 8.4 portd, trisd and latd register s portd is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisd. setting a trisd bit (=1) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisd bit (=0) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latd register reads and writes the latched output value for portd. portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. portd can be configured as an 8-bit wide micro- processor port (parallel slave port), by setting control bit pspmode (pspcon register). in this mode, the input buffers are ttl. see section 9.0 for additional information on the parallel slave port (psp). example 8-4: initializing portd figure 8-7: portd block diagram in i/o port mode clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisd ; set rd3:rd0 as inputs ; rd5:rd4 as outputs ; rd7:rd6 as inputs data bus wr latd wr trisd rd portd data latch tris latch rd trisd schmitt trigger input buffer i/o pin note: i/o pins have diode protection to v dd and v ss . q d ck q d ck en qd en rd latd or wr portd pic18cxx8 ds30475a-page 96 advanced information ? 2000 microchip technology inc. table 8-7: portd functions table 8-8: summary of registers associated with portd name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0. rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1. rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2. rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3. rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4. rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5. rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6. rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd data output register xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 pspcon ibf obf ibov pspmode ? ? ? ? 0000 ---- 0000 ---- legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by portd. ? 2000 microchip technology inc. advanced information ds30475a-page 97 pic18cxx8 8.5 porte, trise and late register s porte is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trise. setting a trise bit (=1) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trise bit (=0) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the late register reads and writes the latched output value for porte. porte is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. porte is multiplexed with several peripheral functions (table 8-9). example 8-5: initializing porte figure 8-8: porte block diagram clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 0x03 ; value used to ; initialize data ; direction movwf trise ; set re1:re0 as inputs ; re7:re2 as outputs peripheral out select data bus wr late wr trise data latch tris latch rd trise q d q ck qd en peripheral data out 0 1 q d q ck p n v dd v ss rd porte peripheral data in i/o pin (1) or wr porte rd late schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . tris override pin override peripheral re0 yes psp re1 yes psp re2 yes psp re3 no ? re4 no ? re5 no ? re6 no ? re7 no ? tris override peripheral enable pic18cxx8 ds30475a-page 98 advanced information ? 2000 microchip technology inc. table 8-9: porte functions table 8-10: summary of registers associated with porte name bit# buffer type function re0/rd bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode. re1/wr bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode. re2/cs bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode. re3 bit3 st input/output port pin. re4 bit4 st input/output port pin. re5 bit5 st input/output port pin. re6 bit6 st input/output port pin. re7/ccp2 bit7 st input/output port pin or capture 2 input/compare 2 output. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffer when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trise porte data direction control register 1111 1111 1111 1111 porte read porte pin/write porte data latch xxxx xxxx uuuu uuuu late read porte data latch/write porte data latch xxxx xxxx uuuu uuuu pspcon ibf obf ibov pspmode ? ? ? ? 0000 ---- 0000 ---- legend: x = unknown, u = unchanged ? 2000 microchip technology inc. advanced information ds30475a-page 99 pic18cxx8 8.6 portf, latf, and trisf registers portf is an 8-bit wide, bi-directional port. the corre- sponding data direction register is trisf. setting a trisf bit (=1) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisf bit (=0) will make the corresponding portf pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latf register reads and writes the latched output value for portf. portf is multiplexed with several analog peripheral functions including the a/d converter inputs and com- parator inputs, outputs, and voltage reference. example 8-6: initializing portf figure 8-9: portf rf1/an6/c2out, rf2/an5/c1out block diagram note 1: on a power-on reset, the rf6:rf0 pins are configured as inputs and read as ? 0 ? . 2: to configure portf as digital i/o, turn off comparators and set adcon1 value. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 0x07 ; movwf cmcon ; turn off comparators movlw 0x0f ; movwf adcon1 ; set portf as digital i/o movlw 0xcf ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf0 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs port/comparator select data bus wr latf wr trisf data latch tris latch rd trisf q d q ck qd en comparator d ata out 0 1 q d q ck p n v dd v ss rd portf i/o pin or wr portf rd latf schmitt trigger note: i/o pins have diode protection to v dd and v ss . analog input mode to a/d converter pic18cxx8 ds30475a-page 100 advanced information ? 2000 microchip technology inc. figure 8-10: rf6:rf3 and rf0 pins block diagram figure 8-11: rf7 pin block diagram table 8-11: portf functions table 8-12: summary of registers associated with portf data bus q d q ck q d q ck qd en p n wr latf wr trisf data latch tris latch rd trisf rd portf v ss v dd i/o pin analog input mode st input buffer to a/d converter or comparator input rd latf or wr portf note: i/o pins have diode protection to v dd and v ss . data bus wr latf wr trisf rd portf data latch tris latch rd trisf schmitt trigger input buffer i/o pin q d ck q d ck en qd en rd latf or wr portf note: i/o pins have diode protection to v dd and v ss . name bit# buffer type function rf0/an5 bit0 st input/output port pin or analog input. rf1/an6/c2out bit1 st input/output port pin or analog input or comparator 2 output. rf2/an7/c1out bit2 st input/output port pin or analog input or comparator 1 output. rf3/an8 bit3 st input/output port pin or analog input or comparator input. rf4/an9 bit4 st input/output port pin or analog input or comparator input. rf5/an10/ cvref bit5 st input/output port pin or analog input or comparator input or comparator reference output. rf6/an11 bit6 st input/output port pin or analog input or comparator input. rf7 bit7 st input/output port pin. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisf portf data direction control register 1111 1111 1111 1111 portf read portf pin / write portf data latch xxxx xxxx uuuu uuuu latf read portf data latch/write portf data latch 0000 0000 uuuu uuuu adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 legend: x = unknown, u = unchanged ? 2000 microchip technology inc. advanced information ds30475a-page 101 pic18cxx8 8.7 portg, latg, and trisg registers portg is a 5-bit wide, bi-directional port. the corre- sponding data direction register is trisg. setting a trisg bit (=1) will make the corresponding portg pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisg bit (=0) will make the corresponding portg pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latg register read and write the latched output value for portg. pins rg0-rg2 on portg are multiplexed with the can peripheral. refer to "can module", section 17.0 for proper settings of trisg when can is enabled. example 8-7: initializing portg figure 8-12: rg0/cantx0 pin block diagram clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 0x04 ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as outputs data latch tris latch rd trisg p v ss q d q ck q d q ck en qd en n v dd 0 1 rd portg wr trisg data bus i/o pin txd endrhi opmode2:opmode0=000 schmitt trigger rd latg wr portg or wr latg opmode2:opmode0 = 000 note: i/o pins have diode protection to v dd and v ss . pic18cxx8 ds30475a-page 102 advanced information ? 2000 microchip technology inc. figure 8-13: rg1/cantx1 pin block diagram figure 8-14: rg2/canrx pin block diagram figure 8-15: rg4:rg3 pins block diagram data latch tris latch rd trisg p v ss q d q ck q d q ck en qd en n v dd 0 1 wr portg or wr trisg data bus rd portg i/o pin 0 1 txd canclk tx1src endrhi opmode2:opmode0=000 tx1en schmitt trigger rd latg wr latg opmode2:opmode0 = 000 note: i/o pins have diode protection to v dd and v ss . data bus wr latg wr trisg rd portg data latch tris latch rd trisg i/o pin q d ck q d ck en qd en rd latg or wr portg canrx schmitt trigger input buffer note: i/o pins have diode protection to v dd and v ss . data bus wr latg wr trisg rd portg data latch tris latch rd trisg schmitt trigger input buffer i/o pin q d ck q d ck en qd en rd latg or wr portg note: i/o pins have diode protection to v dd and v ss . ? 2000 microchip technology inc. advanced information ds30475a-page 103 pic18cxx8 table 8-13: portg functions note: refer to "can module", section 17.0 for usage of can pin functions. table 8-14: summary of registers associated with portg name bit# buffer type function rg0/cantx0 bit0 st input/output port pin or can bus transmit output. rg1/cantx1 bit1 st input/output port pin or can bus complimentary transmit output or can bus bit time clock. rg2/canrx bit2 st input/output port pin or can bus receive input. rg3 bit3 st input/output port pin. rg4 bit4 st input/output port pin. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisg portg data direction control register ---1 1111 ---1 1111 portg read portg pin / write portg data latch ---x xxxx ---u uuuu latg read portg data latch/write portg data latch ---x xxxx ---u uuuu ciocon tx1src tx1en endrhi cancap ? ? ? ? 0000 ---- 0000 ---- legend: x = unknown, u = unchanged pic18cxx8 ds30475a-page 104 advanced information ? 2000 microchip technology inc. 8.8 p orth, lath, and trish registers porth is a 5-bit wide, bi-directional port available only on the pic18c858 devices. the corresponding data direction register is trish. setting a trish bit (=1) will make the corresponding porth pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trish bit (=0) will make the corre- sponding porth pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the lath register read and write the latched output value for porth. pins rh0-rh3 on the pic18c858 are bi-directional i/o pins with st input buffers. pins rh4-rh7 on all devices are multiplexed with a/d converter inputs. figure 8-16: rh3:rh0 pins block diagram example 8-8: initializing porth figure 8-17: rh7:rh4 pins block diagram note: this port is available on pic18c858. note: on a power-on reset, the rh7:rh4 pins are configured as inputs and read as ? 0 ? . data bus wr lath wr trish rd data latch tris latch rd trish schmitt trigger q d q ck qd en q d q ck p n v dd v ss porth i/o pin or wr porth rd lath note: i/o pins have diode protection to v dd and v ss . clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0x0f ; movwf adcon1 ; movlw 0xcf ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs data bus q d q ck q d q ck qd en p n wr lath wr trish data latch tris latch rd trish rd porth v ss v dd i/o pin analog input mode st input buffer to a/d converter rd lath or wr porth note: i/o pins have diode protection to v dd and v ss . ? 2000 microchip technology inc. advanced information ds30475a-page 105 pic18cxx8 table 8-15: porth functions table 8-16: summary of registers associated with porth name bit# buffer type function rh0 bit0 st input/output port pin. rh1 bit1 st input/output port pin. rh2 bit2 st input/output port pin. rh3 bit3 st input/output port pin. rh4/an12 bit4 st input/output port pin or analog input channel 12. rh5/an13 bit5 st input/output port pin or analog input channel 13. rh6/an14 bit6 st input/output port pin or analog input channel 14. rh7/an15 bit7 st input/output port pin or analog input channel 15. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trish porth data direction control register 1111 1111 1111 1111 porth read porth pin/write porth data latch xxxx xxxx uuuu uuuu lath read porth data latch/write porth data latch xxxx xxxx uuuu uuuu adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented pic18cxx8 ds30475a-page 106 advanced information ? 2000 microchip technology inc. 8.9 portj, latj, and trisj registers portj is an 8-bit wide, bi-directional port available only on the pic18c858 devices. the corresponding data direction register is trisj. setting a trisj bit (=1) will make the corresponding portj pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisj bit (=0) will make the corresponding portj pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latj register read and write the latched output value for portj. portj on the pic18c858 is an 8-bit port with schmitt trigger input buffers. each pin is individually config- urable as an input or output. example 8-9: initializing portj figure 8-18: portj block diagram note: this port is available on pic18c858. clrf portj ; initialize portj by ; clearing output ; data latches clrf latj ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as outputs ; rj7:rj6 as inputs data bus wr latj wr trisj data latch tris latch rd trisj q d q ck qd en q d q ck p n v dd v ss rd portj i/o pin or wr portj rd latj schmitt trigger note: i/o pins have diode protection to v dd and v ss . ? 2000 microchip technology inc. advanced information ds30475a-page 107 pic18cxx8 table 8-17: portj functions table 8-18: summary of registers associated with portj name bit# buffer type function rj0 bit0 st/ttl input/output port pin. rj1 bit1 st/ttl input/output port pin. rj2 bit2 st/ttl input/output port pin. rj3 bit3 st/ttl input/output port pin. rj4 bit4 st/ttl input/output port pin. rj5 bit5 st/ttl input/output port pin. rj6 bit6 st/ttl input/output port pin. rj7 bit7 st/ttl input/output port pin. legend: st = schmitt trigger input, ttl = ttl input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisj portj data direction control register 1111 1111 1111 1111 portj read portj pin/write portj data latch xxxx xxxx uuuu uuuu latj read portj data latch/write portj data latch xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged pic18cxx8 ds30475a-page 108 advanced information ? 2000 microchip technology inc. 8.10 portk, latk, and trisk registers portk is an 8-bit wide, bi-directional port available only on the pic18c858 devices. the corresponding data direction register is trisk. setting a trisk bit (=1) will make the corresponding portk pin an input (i.e., put the corresponding output driver in a hi-impedance mode). clearing a trisk bit (=0) will make the corresponding portk pin an output (i.e., put the contents of the output latch on the selected pin). read-modify-write operations on the latk register read and write the latched output value for portk. portk is an 8-bit port with schmitt trigger input buff- ers. each pin is individually configurable as an input or output. example 8-10: initializing portk figure 8-19: portk block diagram table 8-19: portk functions table 8-20: summary of registers associated with portk note: this port is available on pic18c858. clrf portk ; initialize portk by ; clearing output ; data latches clrf latk ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisk ; set rk3:rk0 as inputs ; rk5:rk4 as outputs ; rk7:rk6 as inputs data bus wr latk wr trisk rd portk data latch tris latch rd trisk schmitt trigger input buffer i/o pin q d ck q d ck en qd en rd latk or wr portk note: i/o pins have diode protection to v dd and v ss . name bit# buffer type function rk0 bit0 st input/output port pin. rk1 bit1 st input/output port pin. rk2 bit2 st input/output port pin. rk3 bit3 st input/output port pin. rk4 bit4 st input/output port pin. rk5 bit5 st input/output port pin. rk6 bit6 st input/output port pin. rk7 bit7 st input/output port pin. legend: st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets trisk portk data direction control register 1111 1111 1111 1111 portk read portk pin / write portk data latch xxxx xxxx uuuu uuuu latk read portk data latch/write portk data latch xxxx xxxx uuuu uuuu legend: x = unknown, u = unchanged ? 2000 microchip technology inc. advanced information ds30475a-page 109 pic18cxx8 9.0 parallel slave port the parallel slave port is an 8-bit parallel interface for transferring data between the pic18cxx8 device and an external device. portd operates as an 8-bit wide parallel slave port, or microprocessor port when control bit pspmode (pspcon register) is set. in slave mode, it is asyn- chronously readable and writable by the external world through rd control input pin re0/rd and wr control input pin re1/wr . it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). a write to the psp occurs when both the cs and wr lines are first detected low. a read from the psp occurs when both the cs and rd lines are first detected low. the porte i/o pins become control inputs for the microprocessor port when bit pspmode (pspcon register) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are configured as digital inputs). in this mode, the input buffers are ttl. figure 9-1: portd and porte block diagram (parallel slave port) data bus wr latd rdx pin q d ck en qd en rd portd one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr ttl ttl ttl ttl or wr portd rd latd data latch note: i/o pins have diode protection to v dd and v ss . pic18cxx8 ds30475a-page 110 advanced information ? 2000 microchip technology inc. register 9-1: pspcon register r-0 r-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ibf obf ibov pspmode ? ? ? ? bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3-0 unimplemented : read as ? 0 ? legend r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 111 pic18cxx8 figure 9-2: parallel slave port write waveforms figure 9-3: parallel slave port read waveforms table 9-1: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd port data latch when written; port pins when read xxxx xxxx uuuu uuuu latd latd data output bits xxxx xxxx uuuu uuuu trisd portd data direction bits 1111 1111 1111 1111 porte re7 re6 re5 re4 re3 re2 re1 re0 0000 0000 0000 0000 late late data output bits xxxx xxxx uuuu uuuu trise porte data direction bits 1111 1111 1111 1111 intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ? . shaded cells are not used by the parallel slave port. pic18cxx8 ds30475a-page 112 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 113 pic18cxx8 10.0 timer0 module the timer0 module has the following features: software selectable as an 8-bit or 16-bit timer/counter readable and writable dedicated 8-bit software programmable prescaler clock source selectable to be external or internal interrupt on overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode edge select for external clock register 10-1 shows the timer0 control register (t0con). figure 10-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 10-1 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 10-1: t0con register note: timer0 is enabled on por. r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 114 advanced information ? 2000 microchip technology inc. figure 10-1: timer0 block diagram in 8-bit mode figure 10-2: timer0 block diagram in 16-bit mode note 1: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. 2: i/o pins have diode protection to v dd and v ss . ra4/t0cki t0se 0 1 0 1 pin (2) t0cs (1) f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 t0cki pin (2) t0se 0 1 0 1 t0cs (1) f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l note 1: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. 2: i/o pins have diode protection to v dd and v ss . ? 2000 microchip technology inc. advanced information ds30475a-page 115 pic18cxx8 10.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0l reg- ister is written, the increment is inhibited for the follow- ing two instruction cycles. the user can work around this by writing an adjusted value to the tmr0l register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the ris- ing edge. restrictions on the external clock input are discussed below. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 10.2 pre s caler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g. clrf tmr0, movwf tmr0, bsf tmr0, x .... etc.) will clear the prescaler count. 10.2.1 switching prescaler assignment the prescaler assignment is fully under software con- trol (i.e., it can be changed ? on-the-fly ? during program execution). note: writing to tmr0 when the prescaler is assigned to timer0, will clear the prescaler count but will not change the prescaler assignment. pic18cxx8 ds30475a-page 116 advanced information ? 2000 microchip technology inc. 10.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 reg- ister overflows from ffh to 00h in 8-bit mode or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0if bit must be cleared in soft- ware by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep, since the timer is shut off during sleep. 10.4 16-bit mode timer reads and writes timer0 can be set in 16-bit mode by clearing t0con t08bit. registers tmr0h and tmr0l are used to access 16-bit timer value. tmr0h is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of timer0 (refer to figure 10-1). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this pro- vides the ability to read all 16-bits of timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of buffered value of tmr0h, when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. table 10-1: registers associated with timer0 note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read as ? 0 ? . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module ? s low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module ? s high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ? porta data direction register (1) --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0. ? 2000 microchip technology inc. advanced information ds30475a-page 117 pic18cxx8 11.0 timer1 module the timer1 module timer/counter has the following fea- tures: 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt on overflow from ffffh to 0000h reset from ccp module special event trigger register 11-1 shows the timer1 control register. this register controls the operating mode of the timer1 module as well as contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled/disabled by setting/clearing control bit tmr1on (t1con register). figure 11-1 is a simplified block diagram of the timer1 module. register 11-1: t1con register note: timer1 is disabled on por. r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 unimplemented: read as '0' bit 5-4 t1ckps1:t1ckps0 : timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 118 advanced information ? 2000 microchip technology inc. 11.1 timer1 operation timer1 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con register). when tmr1cs is clear, timer1 increments every instruction cycle. when tmr1cs is set, timer1 incre- ments on every rising edge of the external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer1 also has an internal ? reset input ? . this reset can be generated by the ccp module (section 14.0). figure 11-1: timer1 block diagram figure 11-2: timer1 block diagram: 16-bit read/write mode tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 sleep input f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 tmr1if overflow tmr1 clr ccp special event trigger t1oscen enable oscillator ( 1 ) t1osc interrupt flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. t1osi t13cki/t1oso timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen enable oscillator (1) tmr1if overflow interrupt fosc/4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t13cki/t1oso t1osi tmr1 flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this reduces power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l special event trigger ? 2000 microchip technology inc. advanced information ds30475a-page 119 pic18cxx8 11.2 timer1 oscillator a crystal oscillator circuit is built-in between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit t1oscen (t1con register). the oscillator is a low power oscillator rated up to 200 khz. it will continue to run during sleep. it is primarily intended for a 32 khz crystal. table 11-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. 11.3 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the tmr1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit tmr1if (pir regis- ters). this interrupt can be enabled/disabled by set- ting/clearing tmr1 interrupt enable bit tmr1ie (pie registers). 11.4 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a ? special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion (if the a/d module is enabled). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a spe- cial event trigger from ccp1, the write will take prece- dence. in this mode of operation, the ccpr1h:ccpr1l regis- ters pair, effectively becomes the period register for timer1. 11.5 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 11-2). when the rd16 control bit (t1con registe r ) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16 bits of timer1, without having to determine whether a read of the high byte followed by a read of the low byte is valid, due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writ- able in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. table 11-1: capacitor selection for the alternate oscillator osc type freq c1 c2 lp 32 khz tbd (1) tbd (1) crystal to be tested: 32.768 khz epson c-001r32.768k-a 20 ppm note 1: microchip suggests 33 pf as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: capacitor values are for design guidance only. note: the special event triggers from the ccp1 module will not set interrupt flag bit tmr1if (pir registers). pic18cxx8 ds30475a-page 120 advanced information ? 2000 microchip technology inc. table 11-2: registers associated with timer1 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module. ? 2000 microchip technology inc. advanced information ds30475a-page 121 pic18cxx8 12.0 timer2 module the timer2 module timer has the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr2 match of pr2 ssp module optional use of tmr2 output to gen- erate clock shift register 12-1 shows the timer2 control register. timer2 can be shut off by clearing control bit tmr2on (t2con register) to minimize power consumption. figure 12-1 is a simplified block diagram of the timer2 module. the prescaler and postscaler selection of timer2 are controlled by this register. 12.1 timer2 operation timer2 can be used as the pwm time-base for the pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps1:t2ckps0 (t2con register). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, pir regis- ters). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. register 12-1: t2con register note: timer2 is disabled on por. u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as '0' bit 6-3 toutps3:toutps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 122 advanced information ? 2000 microchip technology inc. 12.2 timer2 interrupt the timer2 module has an 8-bit period register pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 12.3 output of tmr2 the output of tmr2 (before the postscaler) is a clock input to the synchronous serial port module, which optionally uses it to generate the shift clock. figure 12-1: timer2 block diagram table 12-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. to toutps3:toutps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 tmr2 timer2 module ? s register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ? . shaded cells are not used by the timer2 module. ? 2000 microchip technology inc. advanced information ds30475a-page 123 pic18cxx8 13.0 timer3 module the timer3 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr3h and tmr3l) readable and writable (both registers) internal or external clock select interrupt on overflow from ffffh to 0000h reset from ccp module trigger figure 13-1 is a simplified block diagram of the timer3 module. register 13-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp clock source. register 11-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen), which can be a clock source for timer3. register 13-1: t3con register note: timer3 is disabled on por. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 1x = timer3 is the clock source for compare/capture ccp modules 01 = timer3 is the clock source for compare/capture of ccp2, timer1 is the clock source for compare/capture of ccp1 00 = timer1 is the clock source for compare/capture ccp modules bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3) when tmr3cs = 1: 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0: this bit is ignored. timer3 uses the internal clock when tmr3cs = 0. bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t1cki (on the rising edge after the first falling edge) 0 = internal clock (fosc/4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 124 advanced information ? 2000 microchip technology inc. 13.1 timer3 operation timer3 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con register). when tmr3cs = 0, timer3 increments every instruc- tion cycle. when tmr3cs = 1, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi and rc0/t1oso/t1cki pins become inputs. that is, the trisc<1:0> value is ignored. timer3 also has an internal ? reset input ? . this reset can be generated by the ccp module (section 13.0). figure 13-1: timer3 block diagram figure 13-2: timer3 block diagram configured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) tmr3if overflow interrupt fosc/4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. t13cki ccp special trigger t3ccpx clr tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi tmr3 t13cki clr ccp special trigger t3ccpx to timer1 clock input note 1: when the t1oscen bit is cleared, the inverter and feedback resistor are turned off. this eliminates power drain. tmr3h data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l tmr3if overflow interrupt flag bit ? 2000 microchip technology inc. advanced information ds30475a-page 125 pic18cxx8 13.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen bit (t1con register). the oscillator is a low power oscillator rated up to 200 khz. refer to ? timer1 module ? , section 11.0 for timer1 oscillator details. 13.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit tmr3if (pir reg- isters). this interrupt can be enabled/disabled by set- ting/clearing tmr3 interrupt enable bit tmr3ie (pie registers). 13.4 resetting timer3 using a ccp trigger output if the ccp module is configured in compare mode to generate a ? special event trigger" (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. timer3 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l registers pair becomes the period register for timer3. refer to ? capture/compare/pwm (ccp) modules ? , section 14.0 for ccp details. table 13-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp module will not set interrupt flag bit tmr3if (pir registers). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip -0-- 0000 -0-- 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the timer1 module. pic18cxx8 ds30475a-page 126 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 127 pic18cxx8 14.0 capture/compare/pwm (ccp) modules each ccp (capture/compare/pwm) module contains a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register, or as a pwm duty cycle register. table 14-1 shows the timer resources of the ccp module modes. the operation of ccp1 is identical to that of ccp2, with the exception of the special event trigger and the can message timestamp received. (refer to ? can module ? , section 17.0 for can operation.) therefore, operation of a ccp module in the following sections is described with respect to ccp1. table 14-2 shows the interaction of the ccp modules. register 14-1 shows the ccpx control registers (ccpxcon). for the ccp1 module, the register is called ccp1con and for the ccp2 module, the regis- ter is called ccp2con. register 14-1: ccp1con register ccp2con register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit1 and bit0 capture mode: unused compare mode: unused pwm mode : these bits are the two lsbs (bit1 and bit0) of the 10-bit pwm duty cycle. the upper eight bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = capture mode, can message received (ccp1 only) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccp pin low, on compare match force ccp pin high (ccpif bit is set) 1001 = compare mode, initialize ccp pin high, on compare match force ccp pin low (ccpif bit is set) 1010 = compare mode, generate software interrupt on compare match (ccpif bit is set, ccp pin is unaffected) 1011 = compare mode, trigger special event (ccpif bit is set, reset tmr1 or tmr3) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 128 advanced information ? 2000 microchip technology inc. 14.1 ccp1 module capture/compare/pwm register1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. 14.2 ccp2 module capture/compare/pwm register2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. table 14-1: ccp mode - timer resource 14.3 c apture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on pin rc2/ccp1. an event is defined as: every falling edge every rising edge every 4th rising edge every 16th rising edge an event is selected by control bits ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit ccp1if (pir registers) is set. it must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old cap- tured value will be lost. 14.3.1 ccp pin configuration in capture mode, the rc2/ccp1 pin should be config- ured as an input by setting the trisc<2> bit. 14.3.2 timer1/timer3 mode selection the timers used with the capture feature (either timer1 and/or timer3) must be running in timer mode or syn- chronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer used with each ccp module is selected in the t3con register. table 14-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 note: if the rc2/ccp1 is configured as an out- put, a write to the port can cause a capture condition. ccpx mode ccpy mode interaction capture capture tmr1 or tmr3 time-base. time-base can be different for each ccp. capture compare the compare could be configured for the special event trigger, which clears either tmr1 or tmr3, depending upon which time-base is used. compare compare the compare(s) could be configured for the special event trigger, which clears tmr1 or tmr3 depending upon which time-base is used. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none pwm compare none ? 2000 microchip technology inc. advanced information ds30475a-page 129 pic18cxx8 14.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie registers) clear to avoid false interrupts and should clear the flag bit ccp1if, following any such change in operating mode. 14.3.4 ccp prescaler there are four prescaler settings, specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 14-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ? false ? interrupt. 14.3.5 can message received the can capture event occurs when a message is received in either receive buffer. the can module pro- vides a rising edge to the ccp module to cause a cap- ture event. this feature is provided to time-stamp the received can messages. example 14-1: changing between capture prescalers figure 14-1: capture mode operation block diagram clrf ccp1con, f ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp1con ; load ccp1con with ; this value ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if tmr3 enable q ? s ccp1m3:ccp1m0 ccp1 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set flag bit ccp2if tmr3 enable q ? s ccp2m3:ccp2m0 ccp2 pin prescaler 1, 4, 1 6 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1 rxb0if or rxb1if ccp1con<3:0> note: i/o pins have diode protection to v dd and v ss . pic18cxx8 ds30475a-page 130 advanced information ? 2000 microchip technology inc. 14.4 compare mode in compare mode, the 16-bit ccpr1 (ccpr2) register value is constantly compared against either the tmr1 register pair value, or the tmr3 register pair value. when a match occurs, the rc2/ccp1 (rc1/ccp2) pin can have one of the following actions: driven high driven low toggle output (high to low or low to high) remains unchanged the action on the pin is based on the value of control bits ccp1m3:ccp1m0 (ccp2m3:ccp2m0). at the same time, interrupt flag bit ccp1if (ccp2if) is set. 14.4.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate trisc bit. 14.4.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 14.4.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is gen- erated (if enabled). 14.4.4 special event trigger in this mode, an internal hardware trigger is generated, which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccpx resets either the tmr1 or tmr3 register pair. additionally, the ccp2 special event trigger will start an a/d conversion if the a/d module is enabled. figure 14-2: compare mode operation block diagram note: clearing the ccp1con register will force the rc2/ccp1 compare output latch to the default low level. this is not the data latch. note: the special event trigger from the ccp2 module will not set the timer1 or timer3 interrupt flag bits. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if match rc2/ccp1 trisc<2> ccp1m3:ccp1m0 mode select output enable pin special event trigger will: reset timer1 or timer3 (but not set timer1 or timer3 interrupt flag bit) set bit go/done, which starts an a/d conversion (ccp2 only) tmr3h tmr3l t3ccp2 ccpr2h ccpr2l comparator 1 0 t3ccp2 t3ccp1 qs r output logic special event trigger set flag bit ccp2if match rc1/ccp2 trisc<1> ccp2m3:ccp2m0 mode select output enable pin 01 note: i/o pins have diode protection to v dd and v ss . ? 2000 microchip technology inc. advanced information ds30475a-page 131 pic18cxx8 table 14-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1register xxxx xxxx uuuu uuuu t1con rd16 ? t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0-00 0000 u-uu uuuu ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip -0-- 0000 -0-- 0000 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by capture and timer1. pic18cxx8 ds30475a-page 132 advanced information ? 2000 microchip technology inc. 14.5 pwm m o de in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 14-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 14.5.3. figure 14-3: simplified pwm block diagram a pwm output (figure 14-4) has a time-base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 14-4: pwm output 14.5.1 pwm period the pwm period is specified by writing to the pr2 reg- ister. the pwm period can be calculated using the fol- lowing formula: pwm period = [(pr2) + 1] ? 4 t osc (tmr2 prescale value) pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (exception: if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 14.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the following equation is used to calculate the pwm duty cycle in time: pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value) ccpr1l and ccp1con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. when the ccpr1h and 2-bit latch match tmr2, con- catenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp1 pin is cleared. maximum pwm resolution (bits) for a given pwm frequency: note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l (master) ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: 8-bit timer is concatenated with 2-bit internal q clock, or 2 bits of the prescaler, to create 10-bit time-base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 12.0) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a dif- ferent frequency than the pwm output. note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = ? 2000 microchip technology inc. advanced information ds30475a-page 133 pic18cxx8 14.5.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 14-4: example pwm frequencies and resolutions at 40 mhz table 14-5: registers associated with pwm and timer2 pwm frequency 2.44 khz 9.76 khz 39.06 khz 156.3 khz 312.5 khz 416.6 khz timer prescaler (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 5.5 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 tmr2 timer2 module ? s register 0000 0000 0000 0000 pr2 timer2 module ? s period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 ccpr1l capture/compare/pwm register1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip -0-- 0000 -0-- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by pwm and timer2. pic18cxx8 ds30475a-page 134 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 135 pic18cxx8 15.0 master synchronous serial port (mssp) module 15.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface tm (spi) inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode pic18cxx8 ds30475a-page 136 advanced information ? 2000 microchip technology inc. 15.2 control registers the mssp module has three associated registers. these include a status register and two control registers. register 15-1 shows the mssp status register (sspstat), register 15-2 shows the mssp control register 1 (sspcon1), and register 15-3 shows the mssp control register 2 (sspcon2). register 15-1: sspstat register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master m ode 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave m ode smp must be cleared when spi is used in slave mode in i 2 c ma ster or sl ave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select ckp = 0 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck ckp = 1 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c sl ave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen, or acken will indicate if the mssp is in idle mode. ? 2000 microchip technology inc. advanced information ds30475a-page 137 pic18cxx8 bit 1 ua: update address (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c m odes) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit ( i 2 c m ode only) 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 138 advanced information ? 2000 microchip technology inc. register 15-2: sspcon1 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit master mo de: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mo de: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. (must be cleared in software.) 0 = no overflow in i 2 c m ode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a "don ? t care" in transmit mode. (must be cleared in software.) 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output. in spi mode: 1 = enables serial port and configures sck, sdo, sdi, and ss as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins in i 2 c m ode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c sl ave mode: sck release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c ma ster mode unused in this mode ? 2000 microchip technology inc. advanced information ds30475a-page 139 pic18cxx8 bit 3 - 0 sspm3:sspm0: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin. ss pin control enabled. 0101 = spi slave mode, clock = sck pin. ss pin control disabled. ss can be used as i/o pin. 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1) ) 1001 = reserved 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 140 advanced information ? 2000 microchip technology inc. register 15-3: sspcon2 register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c master mode only) in ma ster tr ansmit mode: 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (in i 2 c master mode only) in ma ster re ceive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in ma ster re ceive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sck release control 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled bit (in i 2 c master mode only) 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 141 pic18cxx8 15.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. all four modes of spi are supported. to accomplish communi- cation, typically three pins are used: serial data out (sdo) - rc5/sdo serial data in (sdi) - rc4/sdi/sda serial clock (sck) - rc3/sck/scl/lvoin additionally, a fourth pin may be used when in any slave mode of operation: slave select (ss ) - ra5/ss /an4 15.3.1 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits sspcon1<5:0> and sspstat<7:6>. these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) figure 15-1 shows the block diagram of the mssp module, when in spi mode. figure 15-1: mssp block diagram (spi mode) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr, until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat register), and the interrupt flag bit, sspif (pir regis- ters), are set. this double buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored, and the write collision detect bit, wcol (sspcon1 register), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed successfully. ( ) read write internal data bus sspsr reg sspm3:sspm0 bit0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke sdi sdo ss sck note: i/o pins have diode protection to v dd and v ss . sspbuf reg pic18cxx8 ds30475a-page 142 advanced information ? 2000 microchip technology inc. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full (bf) bit (sspstat register) indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 15-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable, and can only be accessed by addressing the sspbuf reg- ister. additionally, the mssp status register (sspstat register) indicates the various status conditions. 15.3.2 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon1 register), must be set. to reset or reconfig- ure spi mode, clear the sspen bit, re-initialize the sspcon registers, and then set the sspen bit. this configures the sdi, sdo, sck, and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed. that is: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ss must have trisc<4> bit set any serial port function that is not desired may be over- ridden by programming the corresponding data direc- tion (tris) register to the opposite value. example 15-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received (transmit complete)? goto loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit ? 2000 microchip technology inc. advanced information ds30475a-page 143 pic18cxx8 15.3.3 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ? line activity monitor ? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon1 register). this, then, would give waveforms for spi communication as shown in figure 15-2, figure 15-4, and figure 15-5, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 15-2 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 15-2: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 sdi sspif (smp = 1) (smp = 0) (smp = 1) cke = 1) cke = 0) cke = 1) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (cke = 0) (cke = 1) next q4 cycle after q2 pic18cxx8 ds30475a-page 144 advanced information ? 2000 microchip technology inc. 15.3.4 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times, as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 15.3.5 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the mid- dle of a transmitted byte, and becomes a floating output. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to 0. this can be done by either forcing the ss pin to a high level, or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function), since it cannot create a bus conflict. figure 15-3: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled, (sspcon<3:0> = 0100 ) the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 sdo bit7 bit6 bit7 sspif (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss bit0 bit7 bit0 next q4 cycle after q2 ? 2000 microchip technology inc. advanced information ds30475a-page 145 pic18cxx8 figure 15-4: spi mode waveform (slave mode with cke = 0) figure 15-5: spi mode waveform (slave mode with cke = 1) sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif (smp = 0) cke = 0) cke = 0) (smp = 0) write to sspbuf sspsr to sspbuf ss optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit7 bit0 sdo bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sspif (smp = 0) cke = 1) cke = 1) (smp = 0) write to sspbuf sspsr to sspbuf ss required next q4 cycle after q2 pic18cxx8 ds30475a-page 146 advanced information ? 2000 microchip technology inc. 15.3.6 sleep operation in master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from sleep. after the device returns to normal mode, the module will continue to trans- mit/receive data. in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode, and data to be shifted into the spi transmit/receive shift register. when all eight bits have been received, the mssp interrupt flag bit will be set and, if enabled, will wake the device from sleep. 15.3.7 effects of a reset a reset disables the mssp module and terminates the current transfer. 15.3.8 bus mode compatibility table 15-1 shows the compatibility between the stan- dard spi modes and the states of the ckp and cke control bits. table 15-1: spi bus modes there is also a smp bit that controls when the data will be sampled. table 15-2: registers associated with spi operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 trisc portc data direction register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa ? porta data direction register (1) --11 1111 --11 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used by the mssp in spi mode. note 1: bit 6 of porta, lata and trisa are enabled in ecio and rcio oscillator modes only. in all other oscillator modes, they are disabled and read ? 0 ? . ? 2000 microchip technology inc. advanced information ds30475a-page 147 pic18cxx8 15.4 mssp i 2 c o peration the mssp module in i 2 c mode, fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master mode). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer. these are the rc3/sck/scl pin, which is the clock (scl), and the rc4/sdi/sda pin, which is the data (sda). the user must configure these pins as inputs or outputs through the trisc<4:3> bits. the mssp module functions are enabled by setting mssp enable bit sspen (sspcon1 register). figure 15-6: mssp block diagram (i 2 c mode) the mssp module has these six registers for i 2 c oper- ation: mssp control register1 (sspcon1) mssp control register2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer (sspbuf) mssp shift register (sspsr) - not directly accessible mssp address register (sspadd) the sspcon1 register allows control of the i 2 c oper- ation. the sspm3:sspm0 mode selection bits (sspcon1 register) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = osc/4 (sspadd +1) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled i 2 c firmware controlled master operation, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. 15.4.1 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value cur- rently in the sspsr register. if either or both of the following conditions are true, the mssp module will not give this ack pulse: a) the buffer full bit bf (sspcon1 register) was set before the transfer was received. b) the overflow bit sspov (sspcon1 register) was set before the transfer was received. in this event, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir registers) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, is shown in timing parameter #100 and parameter #101. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda note: i/o pins have diode protection to v dd and v ss . pic18cxx8 ds30475a-page 148 advanced information ? 2000 microchip technology inc. 15.4.1.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start con- dition, the eight bits are shifted into the sspsr register. all incoming bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match, and the bf and sspov bits are clear, the following events occur: a) the sspsr register value is loaded into the sspbuf register. b) the buffer full bit bf is set. c) an ack pulse is generated. d) mssp interrupt flag bit sspif (pir registers) is set on the falling edge of the ninth scl pulse (interrupt is generated, if enabled). in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msb) of the first address byte specify if this is a 10-bit address. the r/w bit (sspstat register) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ?1111 0 a9 a8 0? , where a9 and a8 are the two msb ? s of the address. the sequence of events for 10-bit addressing is as fol- lows, with steps 7- 9 for slave-transmitter: 1. receive first (high) byte of address (the sspif, bf and ua bits (sspstat register) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf, and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif. ? 2000 microchip technology inc. advanced information ds30475a-page 149 pic18cxx8 15.4.1.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register. when the address byte overflow condition exists, then no acknowledge (ack ) pulse is given. an overflow con- dition is defined as either bit bf (sspstat register) is set or bit sspov (sspcon1 register) is set. an mssp interrupt is generated for each data transfer byte. flag bit sspif (pir registers) must be cleared in software. the sspstat register is used to determine the status of the byte. 15.4.1.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low. the transmit data must be loaded into the sspbuf register, which also loads the sspsr regis- ter. then pin rc3/sck/scl should be enabled by set- ting bit ckp (sspcon1 register). the master must monitor the scl pin prior to asserting another clock pulse. the slave devices may be holding off the master by stretching the clock. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 15-8). an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. as a slave-transmitter, the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. when the ack is latched by the slave, the slave logic is reset (resets sspstat register) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the transmit data must be loaded into the ssp- buf register, which also loads the sspsr register. pin rc3/sck/scl should be enabled by setting bit ckp. figure 15-7: i 2 c slave mode waveforms for reception (7-bit address) figure 15-8: i 2 c slave mode waveforms for transmission (7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 123456 789 1234 56 7 8 9 1234 bus master term ina tes transfer bit sspov is set because the sspbuf register is still full. cleared in software sspbuf register is read ack receiving data receiving data d0 d1 d2 d3 d4 d5 d6 d7 ack r/w =0 receiving address sspif bf sspov not ack ack is not sent. sda scl sspif bf ckp a7 a6 a5 a4 a3 a2 a1 ack d7 d6 d5 d4 d3 d2 d1 d0 not ack transmitting data r/w = 1 receiving address 123456789 123456789 p cleared in software sspbuf is written in software from ssp interrupt service routine set bit after writing to sspbuf s data in sampled scl held low while cpu responds to sspif (the sspbuf must be written to before the ckp bit can be set) r/w = 0 pic18cxx8 ds30475a-page 150 advanced information ? 2000 microchip technology inc. 15.4.2 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all 0 ? s with r/w = 0. the general call address is recognized (enabled) when the general call enable (gcen) bit is set (sspcon2 register). following a start bit detect, eight bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf bit is set (eighth bit), and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match, and the ua bit is set (sspstat register). if the general call address is sampled when the gcen bit is set, and while the slave is configured in 10-bit address mode; then, the second half of the address is not necessary. the ua bit will not be set, and the slave will begin receiving data after the acknowledge (figure 15-9). figure 15-9: slave mode general call address sequence (7 or 10-bit address) sda scl s sspif bf sspov cleared in software sspbuf is read r/ w = 0 ack general call address address is compared to general call address gcen receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt ? 0 ? ? 1 ? ? 2000 microchip technology inc. advanced information ds30475a-page 151 pic18cxx8 15.4.3 master mode master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset, or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in master mode, the scl and sda lines are manipu- lated by the mssp hardware. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start condition 15.4.4 i 2 c master mode support master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. once master mode is enabled, the user has the following six options: 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmis- sion of data/address. 4. generate a stop condition on sda and scl. 5. configure the i 2 c port to receive data. 6. generate an acknowledge condition at the end of a received byte of data. figure 15-10: mssp block diagram (i 2 c master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to imitate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0 note: i/o pins have diode protection to v dd and v ss . start bit detect stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv pic18cxx8 ds30475a-page 152 advanced information ? 2000 microchip technology inc. 15.4.4.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a trans- fer is ended with a stop condition or with a repeated start condition. since the repeated start condi- tion is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ? . serial data is transmitted eight bits at a time. after each byte is trans- mitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ? . thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received eight bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the begin- ning and end of transmission. the baud rate generator used for the spi mode opera- tion is now used to set the scl clock frequency for either 100 khz, 400 khz, or 1 mhz i 2 c operation. the baud rate generator reload value is contained in the lower 7 bits of the sspadd register. the baud rate generator will automatically begin counting on a write to the sspbuf. once the given operation is complete (i.e., transmission of the last data bit is followed by ack), the internal clock will automatically stop counting and the scl pin will remain in its last state. a typical transmit sequence would go as follows: a) the user generates a start condition by set- ting the start enable (sen) bit (sspcon2 register). b) sspif is set. the mssp module will wait the required start time before any other operation takes place. c) the user loads the sspbuf with the address to transmit. d) address is shifted out the sda pin until all eight bits are transmitted. e) the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit (sspcon2 register). f) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. g) the user loads the sspbuf with eight bits of data. h) data is shifted out the sda pin until all eight bits are transmitted. i) the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit (sspcon2 register). j) the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. k) the user generates a stop condition by setting the stop enable bit pen (sspcon2 register). l) interrupt is generated once the stop condition is complete. ? 2000 microchip technology inc. advanced information ds30475a-page 153 pic18cxx8 15.4.5 baud rate generator in i 2 c master mode, the reload value for the brg is located in the lower 7 bits of the sspadd register (figure 15-11). when the brg is loaded with this value, the brg counts down to 0 and stops until another reload has taken place. the brg count is dec- remented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. if clock arbitration is taking place, for instance, the brg will be reloaded when the scl pin is sampled high (figure 15-12). figure 15-11: baud rate generator block diagram figure 15-12: baud rate generator timing with clock arbitration sspm3:sspm0 brg down counter clkout fosc/4 sspadd<6:0> sspm3:sspm0 scl reload control reload sda scl scl de-asserted but slave holds dx-1 dx brg scl is sampled high, reload takes place and brg starts its count. 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles pic18cxx8 ds30475a-page 154 advanced information ? 2000 microchip technology inc. 15.4.6 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable (sen) bit (sspcon2 register). if the sda and scl pins are sampled high, the baud rate generator is re-loaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low, while scl is high, is the start condition, and causes the s bit (sspstat register) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2 register) will be automatically cleared by hardware, the baud rate gen- erator is suspended leaving the sda line held low and the start condition is complete. 15.4.6.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn ? t occur). figure 15-13: first start bit timing note: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag bclif is set, the start condition is aborted, and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1, at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat) and sets sspif bit ? 2000 microchip technology inc. advanced information ds30475a-page 155 pic18cxx8 15.4.7 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2 register) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins count- ing. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be de-asserted (brought high). when scl is sampled high, the baud rate generator is re-loaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0) for one t brg , while scl is high. following this, the rsen bit (sspcon2 register) will be automat- ically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat register) will be set. the sspif bit will not be set until the baud rate generator has timed-out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 15.4.7.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn ? t occur). figure 15-14: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low to high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data "1". note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here. falling edge of ninth clock end of xmit at completion of start bit, hardware clear rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1, sda = 1, scl(no change) scl = 1 occurs here. t brg t brg t brg and set sspif pic18cxx8 ds30475a-page 156 advanced information ? 2000 microchip technology inc. 15.4.8 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by sim- ply writing a value to the sspbuf register. this action will set the buffer full bit, bf, and allow the baud rate generator to begin counting and start the next transmis- sion. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter 106). scl is held low for one baud rate generator roll over count (t brg ). data should be valid before scl is released high (see data setup time specification parameter 107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next fall- ing edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf bit is cleared and the master releases sda, allowing the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurs, or if data was received properly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is sus- pended until the next data byte is loaded into the ssp- buf, leaving scl low and sda unchanged (figure 15-15). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl, until all seven address bits and the r/w bit, are completed. on the falling edge of the eighth clock, the master will de-assert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2 register). following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf bit is cleared and the baud rate generator is turned off, until another write to the sspbuf takes place, holding scl low and allowing sda to float. 15.4.8.1 bf status flag in transmit mode, the bf bit (sspstat register) is set when the cpu writes to sspbuf, and is cleared when all eight bits are shifted out. 15.4.8.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn ? t occur). wcol must be cleared in software. 15.4.8.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2 register) is cleared when the slave has sent an acknowledge (ack = 0), and is set when the slave does not acknowledge (ack = 1). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 15.4.9 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2 register). the baud rate generator begins counting, and on each rollover, the state of the scl pin changes (high to low/low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the rcen bit is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf bit is automatically cleared. the user can then send an acknowledge bit at the end of reception, by setting the acknowledge sequence enable bit acken (sspcon2 register). 15.4.9.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 15.4.9.2 sspov status flag in receive operation, the sspov bit is set when eight bits are received into the sspsr and the bf bit is already set from a previous reception. 15.4.9.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn ? t occur). note: the mssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded. ? 2000 microchip technology inc. advanced information ds30475a-page 157 pic18cxx8 figure 15-15: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7d6d5d4d3d2d1d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware. s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w pic18cxx8 ds30475a-page 158 advanced information ? 2000 microchip technology inc. figure 15-16: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3>, (rcen = 1) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0, scl = 1 while cpu ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0 ? 2000 microchip technology inc. advanced information ds30475a-page 159 pic18cxx8 15.4.10 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit acken (sspcon2 register). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit (ackdt) is presented on the sda pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is de-asserted (pulled high). when the scl pin is sampled high (clock arbitra- tion), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 15-17). 15.4.10.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn ? t occur). 15.4.11 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2 register). at the end of a receive/transmit, the scl line is held low after the fall- ing edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high, and one t brg (baud rate generator rollover count) later, the sda pin will be de-asserted. when the sda pin is sampled high while scl is high, the p bit (sspstat register) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 15-18). 15.4.11.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the con- tents of the buffer are unchanged (the write doesn ? t occur). figure 15-17: acknowledge sequence waveform note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1, ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software pic18cxx8 ds30475a-page 160 advanced information ? 2000 microchip technology inc. figure 15-18: stop condition receive or transmit mode scl sda sda asserted low before rising edge of clock write to sspcon2 set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat) is set t brg to set up stop condition. ack p t brg pen bit (sspcon2) is cleared by hardware and the sspif bit is set ? 2000 microchip technology inc. advanced information ds30475a-page 161 pic18cxx8 15.4.12 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, de-asserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count, in the event that the clock is held low by an external device (figure 15-19). 15.4.13 sleep operation while in sleep mode, the i 2 c module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 15.4.14 effect of a reset a reset disables the mssp module and terminates the current transfer. figure 15-19: clock arbitration timing in master transmit mode scl sda brg overflow, release scl, if scl = 1 load brg with sspadd<6:0>, and start count brg overflow occurs, release scl, slave device holds scl low. scl = 1 brg starts counting clock high interval. scl line sampled once every machine cycle (t osc 2 4). hold off brg until scl is sampled high. t brg t brg t brg to measure high time interval. pic18cxx8 ds30475a-page 162 advanced information ? 2000 microchip technology inc. 15.4.15 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset, or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat register) is set, or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration, to see if the signal level is the expected output level. this check is performed in hard- ware, with the result placed in the bclif bit. arbitration can be lost in the following states: address transfer data transfer a start condition a repeated start condition an acknowledge condition 15.4.16 multi -master communication, bus collision, and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a '1' on sda, by letting sda float high and another master asserts a '0'. when the scl pin floats high, data should be stable. if the expected data on sda is a '1' and the data sampled on the sda pin = '0', then a bus collision has taken place. the master will set the bus collision interrupt flag (bclif) and reset the i 2 c port to its idle state. (figure 15-20). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf bit is cleared, the sda and scl lines are de-asserted, and the sspbuf can be written to. when the user services the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop, or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are de-asserted, and the respective control bits in the sspcon2 register are cleared. when the user ser- vices the bus collision interrupt service routine, and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the trans- mitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 15-20: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high data doesn ? t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 ? 2000 microchip technology inc. advanced information ds30475a-page 163 pic18cxx8 15.4.16.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 15-21). b) scl is sampled low before sda is asserted low (figure 15-22). during a start condition, both the sda and the scl pins are monitored. if: the sda pin is already low or the scl pin is already low, then: the start condition is aborted, and the bclif flag is set, and the mssp module is reset to its idle state (figure 15-21). the start condition begins with the sda and scl pins de-asserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 15-23). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0, and during this time, if the scl pin is sampled as ? 0 ? , a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 15-21: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1, scl = 1. sda = 0, scl = 1. bclif s sspif sda = 0, scl = 1. sspif and bclif are cleared in software. sspif and bclif are cleared in software. . set bclif, set bclif. start condition. pic18cxx8 ds30475a-page 164 advanced information ? 2000 microchip technology inc. figure 15-22: bus collision during start condition (scl = 0) figure 15-23: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs, set bclif scl = 0 before sda = 0, set sen, enable start sequence if sda = 1, scl = 1 t brg t brg sda = 0, scl = 1 bclif s sspif interrupt cleared in software bus collision occurs, set bclif scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s set sen, enable start sequence if sda = 1, scl = 1 less than t brg t brg sda = 0, scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0, scl = 1 sda pulled low by other master reset brg and assert sda scl pulled low after brg time-out set sspif ? 0 ? ? 2000 microchip technology inc. advanced information ds30475a-page 165 pic18cxx8 15.4.16.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indi- cating that another master is attempting to trans- mit a data ? 1 ? . when the user de-asserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then de-asserted, and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e, another master is attempting to transmit a data ? 0 ? , see figure 15-24). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high to low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condi- tion (figure 15-25). if at the end of the brg time-out both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 15-24: bus collision during a repeated start condition (case 1) figure 15-25: bus collision during repeated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0, set bclif and release sda and scl. cleared in software. '0' '0' sda scl bclif rsen s sspif interrupt cleared in software. scl goes low before sda. set bclif, release sda and scl. t brg t brg ? 0 ? pic18cxx8 ds30475a-page 166 advanced information ? 2000 microchip technology inc. 15.4.16.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been de-asserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is de-asserted, scl is sam- pled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 15-26). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempt- ing to drive a data ? 0 ? (figure 15-27). figure 15-26: bus collision during a stop condition (case 1) figure 15-27: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ? ? 2000 microchip technology inc. advanced information ds30475a-page 167 pic18cxx8 16.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules. (usart is also known as a serial com- munications interface or sci). the usart can be con- figured as a full duplex asynchronous system that can communicate with peripheral devices, such as crt ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices, such as a/d or d/a inte- grated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full duplex) synchronous - master (half duplex) synchronous - slave (half duplex) the spen (rcsta register) and the trisc<7> bits have to be set, and the trisc<6> bit must be cleared, in order to configure pins rc6/tx/ck and rc7/rx/dt as the universal synchronous asynchro- nous receiver transmitter. register 16-1 shows the transmit status and control register (txsta) and register 16-2 shows the receive status and control register (txsta). register 16-1: txsta register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ? brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode don ? t care synchronous mode 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9 : 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen : transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync : usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as '0' bit 2 brgh : high baud rate select bit asynchronous mode 1 = high speed 0 = low speed synchronous mode unused in this mode bit 1 trmt : transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data. can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 168 advanced information ? 2000 microchip technology inc. register 16-2: rcsta register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9 : 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren : single receive enable bit asynchronous mode don ? t care synchronous mode - m aster 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode - s lave unused in this mode bit 4 cren : continuous receive enable bit asynchronous mode 1 = enables continuous receive 0 = disables continuous receive synchronous mode 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden : address detect enable bit asynchronous mode 9-bit (rx9 = 1) 1 = enables address detection, enable interrupt and load of the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received, and ninth bit can be used as parity bit bit 2 ferr : framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr : overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data, can be address/data bit or a parity bit legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 169 pic18cxx8 16.1 usart baud rate generator (brg) the brg supports both the asynchronous and syn- chronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free running 8-bit timer. in asynchronous mode, bit brgh (txsta register) also controls the baud rate. in synchronous mode, bit brgh is ignored. table 16-1 shows the formula for computation of the baud rate for different usart modes, which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 16-1. from this, the error in baud rate can be determined. example 16-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 it may be advantageous to use the high baud rate (brgh = 1), even for slower baud clocks. this is because the f osc /(16(x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before output- ting the new baud rate. 16.1.1 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. example 16-1: calculating baud rate error table 16-1: baud rate formula table 16-2: registers associated with baud rate generator desired baud rate = f osc / (64 (x + 1)) solving for x: x = ( (f osc / desired baud rate) / 64 ) - 1 x = ((16000000 / 9600) / 64) - 1 x = [25.042] = 25 calculated baud rate = 16000000 / (64 (25 + 1)) = 9615 error = (calculated baud rate - desired baud rate) desired baud rate = (9615 - 9600) / 9600 = 0.16% sync brgh = 0 (low speed) brgh = 1 (high speed) 0 1 (asynchronous) baud rate = f osc /(64(x+1)) (synchronous) baud rate = f osc /(4(x+1)) baud rate = f osc /(16(x+1)) na legend: x = value in spbrg (0 to 255) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used by the brg. pic18cxx8 ds30475a-page 170 advanced information ? 2000 microchip technology inc. table 16-3: baud rates for synchronous mode baud rate (kbps) f osc = 40 mhz spbrg value (decimal) 33 mhz spbrg value (decimal) 25 mhz spbrg value (decimal) 20 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- - na- - na - - na- - 1.2na- - na- - na - - na- - 2.4na- - na- - na - - na- - 9.6na- - na- - na - - na- - 19.2 na - - na - - na - - na - - 76.8 76.92 +0.16 129 77.10 +0.39 106 77.16 +0.47 80 76.92 +0.16 64 96 96.15 +0.16 103 95.93 -0.07 85 96.15 +0.16 64 96.15 +0.16 51 300 303.03 +1.01 32 294.64 -1.79 27 297.62 -0.79 20 294.12 -1.96 16 500 500 0 19 485.30 -2.94 16 480.77 -3.85 12 500 0 9 high 10000 - 0 8250 - 0 6250 - 0 5000 - 0 low 39.06 - 255 32.23 - 255 24.41 - 255 19.53 - 255 baud rate (kbps) f osc = 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) 5.0688 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- - na- - na - - na- - 1.2na- - na- - na - - na- - 2.4na- - na- - na - - na- - 9.6 na - - na - - 9.62 +0.23 185 9.60 0 131 19.2 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 19.20 0 65 76.8 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 74.54 -2.94 16 96 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 97.48 +1.54 12 300 307.70 +2.56 12 312.50 +4.17 7 298.35 -0.57 5 316.80 +5.60 3 500 500 0 7 500 0 4 447.44 -10.51 3 422.40 -15.52 2 high 4000 - 0 2500 - 0 1789.80 - 0 1267.20 - 0 low 15.63 - 255 9.77 - 255 6.99 - 255 4.95 - 255 baud rate (kbps) f osc = 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - 0.30 +1.14 26 1.2 na - - na - - 1.20 +0.16 207 1.17 -2.48 6 2.4 na - - na - - 2.40 +0.16 103 2.73 +13.78 2 9.6 9.62 +0.16 103 9.62 +0.23 92 9.62 +0.16 25 8.20 -14.67 0 19.2 19.23 +0.16 51 19.04 -0.83 46 19.23 +0.16 12 na - - 76.8 76.92 +0.16 12 74.57 -2.90 11 83.33 +8.51 2 na - - 96 1000 +4.17 9 99.43 +3.57 8 83.33 -13.19 2 na - - 300 333.33 +11.11 2 298.30 -0.57 2 250 -16.67 0 na - - 500 500 0 1 447.44 -10.51 1 na - - na - - high 1000 - 0 894.89 - 0 250 - 0 8.20 - 0 low 3.91 - 255 3.50 - 255 0.98 - 255 0.03 - 255 ? 2000 microchip technology inc. advanced information ds30475a-page 171 pic18cxx8 table 16-4: baud rates for asynchronous mode (brgh = 0) baud rate (kbps) f osc = 40 mhz spbrg value (decimal) 33 mhz spbrg value (decimal) 25 mhz spbrg value (decimal) 20 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 na - - na - - na - - na - - 2.4 na - - 2.40 -0.07 214 2.40 -0.15 162 2.40 +0.16 129 9.6 9.62 +0.16 64 9.55 -0.54 53 9.53 -0.76 40 9.47 -1.36 32 19.2 18.94 -1.36 32 19.10 -0.54 26 19.53 +1.73 19 19.53 +1.73 15 76.8 78.13 +1.73 7 73.66 -4.09 6 78.13 +1.73 4 78.13 +1.73 3 96 89.29 -6.99 6 103.13 +7.42 4 97.66 +1.73 3 104.17 +8.51 2 300 312.50 +4.17 1 257.81 -14.06 1 na - - 312.50 +4.17 0 500 625 +25.00 0 na - - na - - na - - high 625 - 0 515.63 - 0 390.63 - 0 312.50 - 0 low 2.44 - 255 2.01 - 255 1.53 - 255 1.22 - 255 baud rate (kbps) f osc = 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) 5.0688 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - na - - na - - 1.2 1.20 +0.16 207 1.20 +0.16 129 1.20 +0.23 92 1.20 0 65 2.4 2.40 +0.16 103 2.40 +0.16 64 2.38 -0.83 46 2.40 0 32 9.6 9.62 +0.16 25 9.77 +1.73 15 9.32 -2.90 11 9.90 +3.13 7 19.2 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 19.80 +3.13 3 76.8 83.33 +8.51 2 78.13 +1.73 1 111.86 +45.65 0 79.20 +3.13 0 96 83.33 -13.19 2 78.13 -18.62 1 na - - na - - 300 250 -16.67 0 156.25 -47.92 0 na - - na - - 500na--na- - na- -na-- high 250 - 0 156.25 - 0 111.86 - 0 79.20 - 0 low 0.98 - 255 0.61 - 255 0.44 - 255 0.31 - 255 baud rate (kbps) f osc = 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 0.30 -0.16 207 0.30 +0.23 185 0.30 +0.16 51 0.26 -14.67 1 1.2 1.20 +1.67 51 1.19 -0.83 46 1.20 +0.16 12 na - - 2.4 2.40 +1.67 25 2.43 +1.32 22 2.23 -6.99 6 na - - 9.6 8.93 -6.99 6 9.32 -2.90 5 7.81 -18.62 1 na - - 19.2 20.83 +8.51 2 18.64 -2.90 2 15.63 -18.62 0 na - - 76.8 62.50 -18.62 0 55.93 -27.17 0 na - - na - - 96 na - - na - - na - - na - - 300 na - - na - - na - - na - - 500 na - - na - - na - - na - - high 62.50 - 0 55.93 - 0 15.63 - 0 0.51 - 0 low 0.24 - 255 0.22 - 255 0.06 - 255 0.002 - 255 pic18cxx8 ds30475a-page 172 advanced information ? 2000 microchip technology inc. table 16-5: baud rates for asynchronous mode (brgh = 1) baud rate (kbps) f osc = 40 mhz spbrg value (decimal) 33 mhz spbrg value (decimal) 25 mhz spbrg value (decimal) 20 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- - na- - na- - na- - 1.2na- - na- - na- - na- - 2.4na- - na- - na- - na- - 9.6 na - - 9.60 -0.07 214 9.59 -0.15 162 9.62 +0.16 129 19.2 19.23 +0.16 129 19.28 +0.39 106 19.30 +0.47 80 19.23 +0.16 64 76.8 75.76 -1.36 32 76.39 -0.54 26 78.13 +1.73 19 78.13 +1.73 15 96 96.15 +0.16 25 98.21 +2.31 20 97.66 +1.73 15 96.15 +0.16 12 300 312.50 +4.17 7 294.64 -1.79 6 312.50 +4.17 4 312.50 +4.17 3 500 500 0 4 515.63 +3.13 3 520.83 +4.17 2 416.67 -16.67 2 high 2500 - 0 2062.50 - 0 1562.50 - 0 1250 - 0 low 9.77 - 255 8,06 - 255 6.10 - 255 4.88 - 255 baud rate (kbps) f osc = 16 mhz spbrg value (decimal) 10 mhz spbrg value (decimal) 7.15909 mhz spbrg value (decimal) 5.0688 mhz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3na- - na- - na- - na- - 1.2na- - na- - na- - na- - 2.4 na - - na - - 2.41 +0.23 185 2.40 0 131 9.6 9.62 +0.16 103 9.62 +0.16 64 9.52 -0.83 46 9.60 0 32 19.2 19.23 +0.16 51 18.94 -1.36 32 19.45 +1.32 22 18.64 -2.94 16 76.8 76.92 +0.16 12 78.13 +1.73 7 74.57 -2.90 5 79.20 +3.13 3 96 100 +4.17 9 89.29 -6.99 6 89.49 -6.78 4 105.60 +10.00 2 300 333.33 +11.11 2 312.50 +4.17 1 447.44 +49.15 0 316.80 +5.60 0 500 500 0 1 625 +25.00 0 447.44 -10.51 0 na - - high 1000 - 0 625 - 0 447.44 - 0 316.80 - 0 low 3.91 - 255 2.44 - 255 1.75 - 255 1.24 - 255 baud rate (kbps) f osc = 4 mhz spbrg value (decimal) 3.579545 mhz spbrg value (decimal) 1 mhz spbrg value (decimal) 32.768 khz spbrg value (decimal) kbaud % error kbaud % error kbaud % error kbaud % error 0.3 na - - na - - 0.30 +0.16 207 0.29 -2.48 6 1.2 1.20 +0.16 207 1.20 +0.23 185 1.20 +0.16 51 1.02 -14.67 1 2.4 2.40 +0.16 103 2.41 +0.23 92 2.40 +0.16 25 2.05 -14.67 0 9.6 9.62 +0.16 25 9.73 +1.32 22 8.93 -6.99 6 na - - 19.2 19.23 +0.16 12 18.64 -2.90 11 20.83 +8.51 2 na - - 76.8 na - - 74.57 -2.90 2 62.50 -18.62 0 na - - 96 na - - 111.86 +16.52 1 na - - na - - 300 na - - 223.72 -25.43 0 na - - na - - 500na- - na- - na- - na- - high 250 - 0 55.93 - 0 62.50 - 0 2.05 - 0 low 0.98 - 255 0.22 - 255 0.24 - 255 0.008 - 255 ? 2000 microchip technology inc. advanced information ds30475a-page 173 pic18cxx8 16.2 u sart asynchronous mode in this mode, the usart uses standard non-return-to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8-bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the usart trans- mits and receives the lsb first. the usart ? s transmit- ter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta regis- ter). parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). asynchronous mode is stopped during sleep. asynchronous mode is selected by clearing the sync bit (txsta register). the usart asynchronous module consists of the fol- lowing important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 16.2.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 16-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the tsr register obtains its data from the read/write transmit buffer register (txreg). the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit txif (pir registers) is set. this inter- rupt can be enabled/disabled by setting/clearing enable bit txie (pie registers). flag bit txif will be set, regardless of the state of enable bit txie and can- not be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicated the status of the txreg register, another bit trmt (txsta register) shows the status of the tsr register. status bit trmt is a read only bit, which is set when the tsr register is empty. no inter- rupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr register is empty. steps to follow when setting up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 16.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts trans- mission). figure 16-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ? pic18cxx8 ds30475a-page 174 advanced information ? 2000 microchip technology inc. figure 16-2: asynchronous transmission figure 16-3: asynchronous transmission (back to back) table 16-6: registers associated with asynchronous transmission word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer register empty flag) trmt bit (transmit shift register empty flag) transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous transmission. ? 2000 microchip technology inc. advanced information ds30475a-page 175 pic18cxx8 16.2.2 usart asynchronous receiver the receiver block diagram is shown in figure 16-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f osc . this mode would typi- cally be used in rs-232 systems. steps to follow when setting up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is desired, set bit brgh (section 16.1). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 16.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. steps to follow when setting up an asynchronous reception with address detect enable: 1. initialize the spbrg register for the appropriate baud rate. if a high speed baud rate is required, set the brgh bit. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcif bit will be set when reception is com- plete. the interrupt will be acknowledged if the rcie and gie bits are set. 8. read the rcsta register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 16-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? note: i/o pins have diode protection to v dd and v ss . pic18cxx8 ds30475a-page 176 advanced information ? 2000 microchip technology inc. figure 16-5: asynchronous reception table 16-7: registers associated with asynchronous reception start bit bit7/8 bit1 bit0 bit7/8 bit0 stop bit start bit start bit bit7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as '0'. shaded cells are not used for asynchronous reception. ? 2000 microchip technology inc. advanced information ds30475a-page 177 pic18cxx8 16.3 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta register). in addition, enable bit spen (rcsta register) is set, in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit csrc (txsta register). 16.3.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 16-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register (txreg). the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg is empty and interrupt bit txif (pir registers) is set. the interrupt can be enabled/disabled by setting/clearing enable bit txie (pie registers). flag bit txif will be set, regardless of the state of enable bit txie, and cannot be cleared in software. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit trmt (txsta register) shows the status of the tsr register. trmt is a read only bit, which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the tsr reg- ister is empty. the tsr is not mapped in data memory, so it is not available to the user. steps to follow when setting up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate (section 16.1). 2. enable the synchronous master serial port by setting bits sync, spen, and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. table 16-8: registers associated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master transmission. pic18cxx8 ds30475a-page 178 advanced information ? 2000 microchip technology inc. figure 16-6: synchronous transmission figure 16-7: synchronous transmission (through txen) bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) trmt txen bit ? 1 ? ? 1 ? note: sync master mode; spbrg = ? 0 ? ; continuous transmission of two 8-bit words. word 2 trmt bit write word 1 write word 2 pin pin rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit0 bit1 bit2 bit6 bit7 txen bit ? 2000 microchip technology inc. advanced information ds30475a-page 179 pic18cxx8 16.3.2 usart synchronous master reception once synchronous master mode is selected, reception is enabled by setting either enable bit sren (rcsta register), or enable bit cren (rcsta register). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. steps to follow when setting up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate (section 16.1). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if the enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. table 16-9: registers associated with synchronous master reception figure 16-8: synchronous reception (master mode, sren) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous master reception. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg note: timing diagram demonstrates sync master mode with bit sren = ? 1 ? and bit brgh = ? 0 ? . q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 ? 0 ? q1 q2 q3 q4 pic18cxx8 ds30475a-page 180 advanced information ? 2000 microchip technology inc. 16.4 usart synchronous slave mode synchronous slave mode differs from the master mode, in that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in sleep mode. slave mode is entered by clearing bit csrc (txsta register). 16.4.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. steps to follow when setting up a synchronous slave transmission: 1. enable the synchronous slave serial port by set- ting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 16.4.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of the sleep mode and bit sren, which is a "don ? t care" in slave mode. if receive is enabled by setting bit cren prior to the sleep instruction, then a word may be received during sleep. on completely receiving the word, the rsr register will transfer the data to the rcreg register, and if enable bit rcie bit is set, the interrupt generated will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. steps to follow when setting up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is com- plete. an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. ? 2000 microchip technology inc. advanced information ds30475a-page 181 pic18cxx8 table 16-10: registers associated with synchronous slave transmission table 16-11: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave transmission. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 rcsta spen rx9 sren cren ? ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync adden brgh trmt tx9d 0000 0010 0000 0010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as '0'. shaded cells are not used for synchronous slave reception. pic18cxx8 ds30475a-page 182 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 183 pic18cxx8 17.0 can module 17.1 overview the controller area network (can) module is a serial interface, useful for communicating with other peripher- als or microcontroller devices. this interface/protocol was designed to allow communications within noisy environments. the can module is a communication controller imple- menting the can 2.0 a/b protocol as defined in the bosch specification. the module will support can 1.2, can 2.0a, can2.0b passive, and can 2.0b active versions of the protocol. the module implemen- tation is a full can system. the can specification is not covered within this data sheet. the reader may refer to the bosch can specification for further details. the module features are as follows: ? implementation of the can protocol can1.2, can2.0a and can2.0b standard and extended data frames 0 - 8 bytes data length programmable bit rate up to 1 mbit/sec support for remote frames double buffered receiver with two prioritized received message storage buffers 6 full (standard/extended identifier) acceptance fil- ters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer 2 full acceptance filter masks, one each associ- ated with the high and low priority receive buffers three transmit buffers with application specified prioritization and abort capability programmable wake-up functionality with inte- grated low-pass filter programmable loopback mode supports self-test operation signaling via interrupt capabilities for all can receiver and transmitter error states programmable clock source programmable link to timer module for time-stamping and network synchronization low power sleep mode 17.1.1 overview of the module the can bus module consists of a protocol engine and message buffering and control. the can protocol engine handles all functions for receiving and transmit- ting messages on the can bus. messages are trans- mitted by first loading the appropriate data registers. status and errors can be checked by reading the appropriate registers. any message detected on the can bus is checked for errors and then matched against filters to see if it should be received and stored in one of the 2 receive registers. the can module supports the following frame types: standard data frame extended data frame remote frame error frame overload frame reception interframe space pic18cxx8 ds30475a-page 184 advanced information ? 2000 microchip technology inc. 17.1.2 transmit/receive buffers the pic18cxx8 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a total of six acceptance filters. figure 17-1 is a block diagram of these buffers and their connection to the protocol engine. figure 17-1: can buffers and protocol engine block diagram acceptance filter rxf2 r x b 1 a c c e p t a c c e p t identifier data field data field identifier acceptance mask rxm1 acceptance filter rxf3 acceptance filter rxf4 acceptance filter rxf5 m a b acceptance mask rxm0 acceptance filter rxf0 acceptance filter rxf1 r x b 0 msgreq txb2 txabt txlarb txerr mtxbuff message message queue control transmit byte sequencer msgreq txb1 txabt txlarb txerr mtxbuff message msgreq txb0 txabt txlarb txerr mtxbuff message receive shift transmit shift receive error transmit error protocol rxerrcnt txerrcnt errpas busoff finite state machine counter counter transmit logic bit timing logic tx rx bit timing generator protocol engine buffers crc check crc generator ? 2000 microchip technology inc. advanced information ds30475a-page 185 pic18cxx8 17.2 control registers for the can module there are many registers associated with the can module. descriptions of these registers are grouped into sections. these sections are: control and status registers transmit buffer registers receive buffer registers baud rate control registers interrupt status and control registers 17.2.1 can control and status registers this section shows the can control and status registers. register 17-1: cancon ? can control register note: not all can registers are available in the access bank. r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 reqop2 reqop1 reqop0 abat win2 win1 win0 ? bit 7 bit 0 bit 7-5 reqop2:reqop0: request can operation mode bits 1xx = request configuration mode 011 = request listen only mode 010 = request loopback mode 001 = request disable mode 000 = request normal mode bit 4 abat: abort all pending transmissions bit 1 = abort all pending transmissions (in all transmit buffers) 0 = transmissions proceeding as normal bit 3-1 win2:win0: window address bits this selects which of the can buffers to switch into the access bank area. this allows access to the buffer registers from any data memory bank. after a frame has caused an interrupt, the icode2:icode0 bits can be copied to the win2:win0 bits to select the correct buffer. see example 17-1 for code example. 111 = receive buffer 0 110 = receive buffer 0 101 = receive buffer 1 100 = transmit buffer 0 011 = transmit buffer 1 010 = transmit buffer 2 001 = receive buffer 0 000 = receive buffer 0 bit 0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 186 advanced information ? 2000 microchip technology inc. register 17-2: canstat ? can status register r-1 r-0 r-0 u-0 r-0 r-0 r-0 u-0 opmode2 opmode1 opmode0 ? icode2 icode1 icode0 ? bit 7 bit 0 bit 7-5 opmode2:opmode0: operation mode status bits 111 = reserved 110 = reserved 101 = reserved 100 = configuration mode 011 = listen only mode 010 = loopback mode 001 = disable mode 000 = normal mode note: before the device goes into sleep mode, select disable mode. bit 4 unimplemented: read as ? 0 ? bit 3-1 icode2:icode0: interrupt code bits when an interrupt occurs, a prioritized coded interrupt value will be present in the icode2:icode0 bits. these codes indicate the source of the interrupt. the icode2:icode0 bits can be copied to the win2:win0 bits to select the correct buffer to map into the access bank area. see example 17-1 for code example. 111 = wake-up on interrupt 110 = rxb0 interrupt 101 = rxb1 interrupt 100 = txb0 interrupt 011 = txb1 interrupt 010 = txb2 interrupt 001 = error interrupt 000 = no interrupt bit 0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 187 pic18cxx8 example 17-1: win and icode bits usage in interrupt service routine to access tx/rx buffers ; save application required context. ; poll interrupt flags and determine source of interrupt ; this was found to be can interrupt ; tempcancon and tempcanstat are variables defined in access bank low movff cancon, tempcancon ; save cancon.win bits ; this is required to prevent cancon ; from corrupting can buffer access ; in-progress while this interrupt ; occurred movff canstat, tempcanstat ; save canstat register ; this is required to make sure that ; we use same canstat value rather ; than one changed by another can ; interrupt. movf tempcanstat, w ; retrieve icode bits andlw b?00001110? addwf pcl, f ; perform computed goto ; to corresponding interrupt cause bra nointerrupt ; 000 = no interrupt bra errorinterrupt ; 001 = error interrupt bra txb2interrupt ; 010 = txb2 interrupt bra txb1interrupt ; 011 = txb1 interrupt bra txb0interrupt ; 100 = txb0 interrupt bra rxb1interrupt ; 101 = rxb1 interrupt bra rxb0interrupt ; 110 = rxb0 interrupt ; 111 = wake-up on interrupt wakeupinterrupt bcf pir3, wakif ; clear the interrupt flag ; ; user code to handle wake-up procedure ; ; ; continue checking for other interrupt source or return from here ? nointerrupt ? ; pc should never vector here. user may ; place a trap such as infinite loop or pin/port ; indication to catch this error. errorinterrupt bcf pir3, errif ; clear the interrupt flag ? ; handle error. retfie txb2interrupt bcf pir3, txb2if ; clear the interrupt flag goto accessbuffer txb1interrupt bcf pir3, txb1if ; clear the interrupt flag goto accessbuffer txb0interrupt bcf pir3, txb0if ; clear the interrupt flag goto accessbuffer rxb1interrupt bcf pir3, rxb1if ; clear the interrupt flag goto accessbuffer pic18cxx8 ds30475a-page 188 advanced information ? 2000 microchip technology inc. rxb0interrupt bcf pir3, rxb0if ; clear the interrupt flag goto accessbuffer accessbuffer ; this is either tx or rx interrupt ; copy cancon.icode bits to canstat.win bits movf tempcancon, w ; clear cancon.win bits before copying ; new ones. andlw b ? 11110001 ? ; use previously saved cancon value to ; make sure same value. movwf tempcancon ; copy masked value back to tempcancon movf tempcanstat, w ; retrieve icode bits andlw b ? 00001110 ? ; use previously saved canstat value ; to make sure same value. iorwf tempcancon ; copy icode bits to win bits. movff tempcancon, cancon ; copy the result to actual cancon ; access current buffer ? ; your code ; restore cancon.win bits movf cancon, w ; preserve current non win bits andlw b ? 11110001 ? iorwf tempcancon ; restore original win bits ; do not need to restore canstat - it is read-only register. ; return from interrupt or check for another module interrupt source ? 2000 microchip technology inc. advanced information ds30475a-page 189 pic18cxx8 register 17-3: comstat ? communication status register r/c-0 r/c-0 r-0 r-0 r-0 r-0 r-0 r-0 rxb0ovfl rxb1ovfl txbo txbp rxbp txwarn rxwarn ewarn bit 7 bit 0 bit 7 rxb0ovfl: receive buffer 0 overflow bit 1 = receive buffer 0 overflowed 0 = receive buffer 0 has not overflowed bit 6 rxb1ovfl: receive buffer 1 overflow bit 1 = receive buffer 1 overflowed 0 = receive buffer 1 has not overflowed bit 5 txb0: transmitter bus off bit 1 = transmit error counter >255 0 = transmit error counter 255 bit 4 txbp: transmitter bus passive bit 1 = transmission error counter >127 0 = transmission error counter 127 bit 3 rxbp: receiver bus passive bit 1 = receive error counter >127 0 = receive error counter 127 bit 2 txwarn: transmitter warning bit 1 = transmit error counter >95 0 = transmit error counter 95 bit 1 rxwarn: receiver warning bit 1 = receive error counter >95 0 = receive error counter 95 bit 0 ewarn: error warning bit this bit is a flag of the rxwarn and txwarn bits 1 = the rxwarn or the txwarn bits are set 0 = neither the rxwarn or the txwarn bits are set legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 190 advanced information ? 2000 microchip technology inc. 17.2.2 can transmit buffer registers this section describes the can transmit buffer register and the associated transmit buffer control registers. register 17-4: txbncon ? transmit buffer n control register register 17-5: txbnsidh: transmit buffer n standard identifier high byte register u-0 r-0 r-0 r-0 r/w-0 u-0 r/w-0 r/w-0 ? txabt txlarb txerr txreq ? txpri1 txpri0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 txabt: transmission aborted status bit 1 = message was aborted 0 = message was not aborted bit 5 txlarb: transmission lost arbitration status bit 1 = message lost arbitration while being sent 0 = message did not lose arbitration while being sent bit 4 txerr: transmission error detected status bit 1 = a bus error occurred while the message was being sent 0 = a bus error did not occur while the message was being sent bit 3 txreq: transmit request status bit 1 = requests sending a message. clears the txabt, tlarb, and txerr bits 0 = automatically cleared when the message is successfully sent note: clearing this bit in software, while the bit is set, will request a message abort. bit 2 unimplemented: read as ? 0 ? bit 1-0 txpri1:txpri0: transmit priority bits 11 = priority level 3 (highest priority) 10 = priority level 2 01 = priority level 1 00 = priority level 0 (lowest priority) note: these bits set the order in which transmit buffer will be transferred. they do not alter can message identifier. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier bits, if exide = 0 (txbnsid register). extended identifier bits eid28:eid21, if exide = 1. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 191 pic18cxx8 register 17-6: txbnsidl ? transmit buffer n standard identifier low byte register register 17-7: txbneidh ? transmit buffer n extended identifier high byte register register 17-8: txbneidl ? transmit buffer n extended identifier low byte register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid2 sid1 sid0 ? exide ? eid17 eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier bits, if exide = 0. extended identifier bits eid20:eid18, if exide = 1. bit 4 unimplemented: read as ? 0 ? bit 3 exide: extended identifier enable bit 1 = message will transmit extended id, sid10:sid0 becomes eid28:eid18 0 = message will transmit standard id, eid17:eid0 are ignored bit 2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 192 advanced information ? 2000 microchip technology inc. register 17-9: txbndm ? transmit buffer n data field byte m register register 17-10: txbndlc ? transmit buffer n data length code register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x txbndm7 txbndm6 txbndm5 txbndm4 txbndm3 txbndm2 txbndm1 txbndm0 bit 7 bit 0 bit 1-0 txbndm7:txbndm0: transmit buffer n data field byte m bits (where 0 n<3 and 0 pic18cxx8 ds30475a-page 194 advanced information ? 2000 microchip technology inc. 17.2.3 can receive buffer registers this section shows the receive buffer registers with its associated control registers. register 17-12: rxb0con ? receive buffer 0 control register r/c-0 r/w-0 r/w-0 u-0 r-0 r/w-0 r-0 r/w-0 rxful rxm1 rxm0 ? rxrtrro rxb0dben jtoff filhit0 bit 7 bit 0 bit 7 rxful: receive full status bit 1 = receive buffer contains a received message 0 = receive buffer is open to receive a new message note: this bit is set by the can module and should be cleared by software after the buffer is read. bit 6-5 rxm1:rxm0: receive buffer mode bits 11 = receive all messages (including those with errors) 10 = receive only valid messages with extended identifier 01 = receive only valid messages with standard identifier 00 = receive all valid messages bit 4 unimplemented: read as ? 0 ? bit 3 rxrtrro: receive remote transfer request read only bit 1 = remote transfer request 0 = no remote transfer request bit 2 rxb0dben: receive buffer 0 double buffer enable bit 1 = receive buffer 0 overflow will write to receive buffer 1 0 = no receive buffer 0 overflow to receive buffer 1 bit 1 jtoff: jump table offset bit (read only copy of rx0dben) 1 = allows jump table offset between 6 and 7 0 = allows jump table offset between 1 and 0 note: this bit allows same filter jump table for both rxb0con and rxb1con. bit 0 filhit0: filter hit bit this bit indicates which acceptance filter enabled the message reception into receive buffer 0 1 = acceptance filter 1 (rxf1) 0 = acceptance filter 0 (rxf0) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 195 pic18cxx8 register 17-13: rxb1con ? receive buffer 1 control register register 17-14: rxbnsidh ? receive buffer n standard identifier high byte register r/c-0 r/w-0 r/w-0 u-0 r-0 r-0 r-0 r-0 rxful rxm1 rxm0 ? rxrtrro filhit2 filhit1 filhit0 bit 7 bit 0 bit 7 rxful: receive full status bit 1 = receive buffer contains a received message 0 = receive buffer is open to receive a new message note: this bit is set by the can module and should be cleared by software after the buffer is read. bit 6-5 rxm1:rxm0: receive buffer mode bits 11 = receive all messages (including those with errors) 10 = receive only valid messages with extended identifier 01 = receive only valid messages with standard identifier 00 = receive all valid messages bit 4 unimplemented: read as ? 0 ? bit 3 rxrtrro: receive remote transfer request bit (read only) 1 = remote transfer request 0 = no remote transfer request bit 2-0 filhit2:filhit0: filter hit bits these bits indicate which acceptance filter enabled the last message reception into receive buffer 1. 111 = reserved 110 = reserved 101 = acceptance filter 5 (rxf5) 100 = acceptance filter 4 (rxf4) 011 = acceptance filter 3 (rxf3) 010 = acceptance filter 2 (rxf2) 001 = acceptance filter 1 (rxf1) only possible when rxb0dben bit is set 000 = acceptance filter 0 (rxf0) only possible when rxb0dben bit is set legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier bits, if exid = 0 (rxbnsidl register). extended identifier bits eid28:eid21, if exid = 1. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 196 advanced information ? 2000 microchip technology inc. register 17-15: rxbnsidl ? receive buffer n standard identifier low byte register register 17-16: rxbneidh ? receive buffer n extended identifier high byte register register 17-17: rxbneidl ? receive buffer n extended identifier low byte register r/w-x r/w-x r/w-x r/w-x r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 srr exid ? eid17 eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier bits, if exid = 0. extended identifier bits eid20:eid18, if exid = 1. bit 4 srr: substitute remove request bit (only when exid = ? 1 ? ) 1 = remote transfer request occurred 0 = no remote transfer request occurred bit 3 exid: extended identifier bit 1 = received message is an extended data frame, sid10:sid0 are eid28:eid18 0 = received message is a standard data frame bit 2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 197 pic18cxx8 register 17-18: rxbndlc ? receive buffer n data length code register register 17-19: rxbndm ? receive buffer n data field byte m register u-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? rxrtr rb1 rb0 dlc3 dlc2 dlc1 dlc0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 rxrtr: receiver remote transmission request bit 1 = remote transfer request 0 = no remote transfer request bit 5 rb1: reserved bit 1 reserved by can spec and read as ? 0 ? bit 4 rb0: reserved bit 0 reserved by can spec and read as ? 0 ? bit 3-0 dlc3:dlc0: data length code bits 1111 = invalid 1110 = invalid 1101 = invalid 1100 = invalid 1011 = invalid 1010 = invalid 1001 = invalid 1000 = data length = 8 bytes 0111 = data length = 7 bytes 0110 = data length = 6 bytes 0101 = data length = 5 bytes 0100 = data length = 4 bytes 0011 = data length = 3 bytes 0010 = data length = 2 bytes 0001 = data length = 1 bytes 0000 = data length = 0 bytes legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rxbndm7 rxbndm6 rxbndm5 rxbndm4 rxbndm3 rxbndm2 rxbndm1 rxbndm0 bit 7 bit 0 bit 7-0 rxbndm7:rxbndm0: receive buffer n data field byte m bits (where 0 n<1 and 0 ? 2000 microchip technology inc. advanced information ds30475a-page 199 pic18cxx8 17.2.4 message acceptance filters this subsection describes the message acceptance filters. register 17-21: rxfnsidh ? receive acceptance filter n standard identifier filter high byte register 17-22: rxfnsidl ? receive acceptance filter n standard identifier filter low byte register 17-23: rxfneidh ? receive acceptance filter n extended identifier high byte r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier filter bits, if exiden = 0. extended identifier filter bits eid28:eid21, if exiden = 1, legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x u-0 r/w-x u-0 r/w-x r/w-x sid2 sid1 sid0 ? exiden ?eid17eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier filter bits, if exiden = 0. extended identifier filter bits eid20:eid18, if exiden = 0. bit 4 unimplemented: read as ?0? bit 3 exiden: extended identifier filter enable bit 1 = filter will only accept extended id messages 0 = filter will only accept standard id messages bit 2 unimplemented: read as ?0? bit 1-0 eid17:eid16: extended identifier filter bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 7-0 eid15:eid8: extended identifier filter bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 200 advanced information ? 2000 microchip technology inc. register 17-24: rxfneidl ? receive acceptance filter n extended identifier low byte register register 17-25: rxmnsidh ? receive acceptance mask n standard identifier mask high byte register register 17-26: rxmnsidl ? receive acceptance mask n standard identifier mask low byte register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 7-0 eid7:eid0: extended identifier filter bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sid10 sid9 sid8 sid7 sid6 sid5 sid4 sid3 bit 7 bit 0 bit 7-0 sid10:sid3: standard identifier mask bits, or extended identifier mask bits eid28:eid21 legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x u-0 u-0 u-0 r/w-x r/w-x sid2 sid1 sid0 ? ? ? eid17 eid16 bit 7 bit 0 bit 7-5 sid2:sid0: standard identifier mask bits, or extended identifier mask bits eid20:eid18 bit 4-2 unimplemented: read as ? 0 ? bit 1-0 eid17:eid16: extended identifier mask bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 201 pic18cxx8 register 17-27: rxmneidh ? receive acceptance mask n extended identifier mask high byte register register 17-28: rxmneidl ? receive acceptance mask n extended identifier mask low byte register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid15 eid14 eid13 eid12 eid11 eid10 eid9 eid8 bit 7 bit 0 bit 1-0 eid15:eid8: extended identifier mask bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x eid7 eid6 eid5 eid4 eid3 eid2 eid1 eid0 bit 7 bit 0 bit 1-0 eid7:eid0: extended identifier mask bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 202 advanced information ? 2000 microchip technology inc. 17.2.5 can baud rate registers this subsection describes the can baud rate registers. register 17-29: brgcon1 ? baud rate control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 bit 7 bit 0 bit 7-6 sjw1:sjw0: synchronized jump width bits 11 = synchronization jump width time = 4 x t q 10 = synchronization jump width time = 3 x t q 01 = synchronization jump width time = 2 x t q 00 = synchronization jump width time = 1 x t q bit 5-0 brp5:brp0: baud rate prescaler bits 111111 = t q = (2 x 64)/f osc 111110 = t q = (2 x 63)/f osc : : 000001 = t q = (2 x 2)/f osc 000000 = t q = (2 x 1)/f osc legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: this register is only accessible in configuration mode. ? 2000 microchip technology inc. advanced information ds30475a-page 203 pic18cxx8 register 17-30: brgcon2 ? baud rate control register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 seg2phts sam seg1ph2 seg1ph1 seg1ph0 prseg2 prseg1 prseg0 bit 7 bit 0 bit 7 seg2phts: phase segment 2 time select bit 1 = freely programmable 0 = maximum of pheg1 or information processing time (ipt), whichever is greater bit 6 sam: sample of the can bus line bit 1 = bus line is sampled three times prior to the sample point 0 = bus line is sampled once at the sample point bit 5-3 seg1ph2:seg1ph0: phase segment 1 bits 111 = phase segment 1 time = 8 x t q 110 = phase segment 1 time = 7 x t q 101 = phase segment 1 time = 6 x t q 100 = phase segment 1 time = 5 x t q 011 = phase segment 1 time = 4 x t q 010 = phase segment 1 time = 3 x t q 001 = phase segment 1 time = 2 x t q 000 = phase segment 1 time = 1 x t q bit 2-0 prseg2:prseg0: propagation time select bits 111 = propagation time = 8 x t q 110 = propagation time = 7 x t q 101 = propagation time = 6 x t q 100 = propagation time = 5 x t q 011 = propagation time = 4 x t q 010 = propagation time = 3 x t q 001 = propagation time = 2 x t q 000 = propagation time = 1 x t q legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: this register is only accessible in configuration mode. pic18cxx8 ds30475a-page 204 advanced information ? 2000 microchip technology inc. register 17-31: brgcon3 ? baud rate control register 3 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? wakfil ? ? ? seg2ph2 seg2ph1 seg2ph0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 wakfil: selects can bus line filter for wake-up bit 1 = use can bus line filter for wake-up 0 = can bus line filter is not used for wake-up bit 5-3 unimplemented: read as ? 0 ? bit 2-0 seg2ph2:seg2ph0: phase segment 2 time select bits 111 = phase segment 2 time = 8 x t q 110 = phase segment 2 time = 7 x t q 101 = phase segment 2 time = 6 x t q 100 = phase segment 2 time = 5 x t q 011 = phase segment 2 time = 4 x t q 010 = phase segment 2 time = 3 x t q 001 = phase segment 2 time = 2 x t q 000 = phase segment 2 time = 1 x t q note: ignored if seg2phts bit is clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 205 pic18cxx8 17.2.6 can module i/o control register this subsection describes the can module i/o control register. register 17-32: ciocon ? can i/o control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 tx1src tx1en endrhi cancap ? ? ? ? bit 7 bit 0 bit 7 tx1src : can tx1 pin data source 1 = can tx1 pin will output the can clock 0 = can tx1 pin will output txd bit 6 tx1en: can tx1 pin enable 1 = can tx1 pin will output txd or can clock 0 = can tx1 pin will have digital i/o function bit 5 endrhi: enable drive high 1 = can tx0, can tx1 pins will drive v dd when recessive 0 = can tx0, can tx1 pins will tri-state when recessive bit 4 cancap: can message receive capture enable 1 = enable can capture 0 = disable can capture bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 206 advanced information ? 2000 microchip technology inc. 17.2.7 can interrupt registers register 17-33: pir3 ? peripheral interrupt flag register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irxif wakif errif txb2if txb1if txb0if rxb1if rxb0if bit 7 bit 0 bit 7 irxif: can invalid received message interrupt flag bit 1 = an invalid message has occurred on the can bus 0 = no invalid message on can bus bit 6 wakif: can bus activity wake-up interrupt flag bit 1 = activity on can bus has occurred 0 = no activity on can bus bit 5 errif: can bus error interrupt flag bit 1 = an error has occurred in the can module (multiple sources) 0 = no can module errors bit 4 txb2if: can transmit buffer 2 interrupt flag bit 1 = transmit buffer 2 has completed transmission of a message, and may be re-loaded 0 = transmit buffer 2 has not completed transmission of a message bit 3 txb1if: can transmit buffer 1 interrupt flag bit 1 = transmit buffer 1 has completed transmission of a message, and may be re-loaded 0 = transmit buffer 1 has not completed transmission of a message bit 2 txb0if: can transmit buffer 0 interrupt flag bit 1 = transmit buffer 0 has completed transmission of a message, and may be re-loaded 0 = transmit buffer 0 has not completed transmission of a message bit 1 rxb1if: can receive buffer 1 interrupt flag bit 1 = receive buffer 1 has received a new message 0 = receive buffer 1 has not received a new message bit 0 rxb0if: can receive buffer 0 interrupt flag bit 1 = receive buffer 0 has received a new message 0 = receive buffer 0 has not received a new message legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 207 pic18cxx8 register 17-34: pie3 ? peripheral interrupt enable register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irxie wakie errie txb2ie txb1ie txb0ie rxb1ie rxb0ie bit 7 bit 0 bit 7 irxie: can invalid received message interrupt enable bit 1 = enable invalid message received interrupt 0 = disable invalid message received interrupt bit 6 wakie: can bus activity wake-up interrupt enable bit 1 = enable bus activity wake-up interrupt 0 = disable bus activity wake-up interrupt bit 5 errie: can bus error interrupt enable bit 1 = enable can bus error interrupt 0 = disable can bus error interrupt bit 4 txb2ie: can transmit buffer 2 interrupt enable bit 1 = enable transmit buffer 2 interrupt 0 = disable transmit buffer 2 interrupt bit 3 txb1ie: can transmit buffer 1 interrupt enable bit 1 = enable transmit buffer 1 interrupt 0 = disable transmit buffer 1 interrupt bit 2 txb0ie: can transmit buffer 0 interrupt enable bit 1 = enable transmit buffer 0 interrupt 0 = disable transmit buffer 0 interrupt bit 1 rxb1ie: can receive buffer 1 interrupt enable bit 1 = enable receive buffer 1 interrupt 0 = disable receive buffer 1 interrupt bit 0 rxb0ie: can receive buffer 0 interrupt enable bit 1 = enable receive buffer 0 interrupt 0 = disable receive buffer 0 interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 208 advanced information ? 2000 microchip technology inc. register 17-35: ipr3 ? peripheral interrupt priority register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 irxip wakip errip txb2ip txb1ip txb0ip rxb1ip rxb0ip bit 7 bit 0 bit 7 irxip: can invalid received message interrupt priority bit 1 = high priority 0 = low priority bit 6 wakip: can bus activity wake-up interrupt priority bit 1 = high priority 0 = low priority bit 5 errip: can bus error interrupt priority bit 1 = high priority 0 = low priority bit 4 txb2ip: can transmit buffer 2 interrupt priority bit 1 = high priority 0 = low priority bit 3 txb1ip: can transmit buffer 1 interrupt priority bit 1 = high priority 0 = low priority bit 2 txb0ip: can transmit buffer 0 interrupt priority bit 1 = high priority 0 = low priority bit 1 rxb1ip: can receive buffer 1 interrupt priority bit 1 = high priority 0 = low priority bit 0 rxb0ip: can receive buffer 0 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 209 pic18cxx8 table 17-1: can controller register map note: shaded registers are available in access bank low area while the rest are available in bank 15. address name address name address name address name f7fh f5fh f3fh f1fh rxm1eidl f7eh f5eh canstat f3eh canstat f1eh rxm1eidh f7dh f5dh rxb1d7 f3dh txb1d7 f1dh rxm1sidl f7ch f5ch rxb1d6 f3ch txb1d6 f1ch rxm1sidh f7bh f5bh rxb1d5 f3bh txb1d5 f1bh rxm0eidl f7ah f5ah rxb1d4 f3ah txb1d4 f1ah rxm0eidh f79h f59h rxb1d3 f39h txb1d3 f19h rxm0sidl f78h f58h rxb1d2 f38h txb1d2 f18h rxm0sidh f77h f57h rxb1d1 f37h txb1d1 f17h rxf5eidl f76h txerrcnt f56h rxb1d0 f36h txb1d0 f16h rxf5eidh f75h rxerrcnt f55h rxb1dlc f35h txb1dlc f15h rxf5sidl f74h comstat f54h rxb1eidl f34h txb1eidl f14h rxf5sidh f73h ciocon f53h rxb1eidh f33h txb1eidh f13h rxf4eidl f72h brgcon3 f52h rxb1sidl f32h txb1sidl f12h rxf4eidh f71h brgcon2 f51h rxb1sidh f31h txb1sidh f11h rxf4sidl f70h brgcon1 f50h rxb1con f30h txb1con f10h rxf4sidh f6fh cancon f4fh f2fh f0fh rxf3eidl f6eh canstat f4eh canstat f2eh canstat f0eh rxf3eidh f6dh rxb0d7 f4dh txb0d7 f2dh txb2d7 f0dh rxf3sidl f6ch rxb0d6 f4ch txb0d6 f2ch txb2d6 f0ch rxf3sidh f6bh rxb0d5 f4bh txb0d5 f2bh txb2d5 f0bh rxf2eidl f6ah rxb0d4 f4ah txb0d4 f2ah txb2d4 f0ah rxf2eidh f69h rxb0d3 f49h txb0d3 f29h txb2d3 f09h rxf2sidl f68h rxb0d2 f48h txb0d2 f28h txb2d2 f08h rxf2sidh f67h rxb0d1 f47h txb0d1 f27h txb2d1 f07h rxf1eidl f66h rxb0d0 f46h txb0d0 f26h txb2d0 f06h rxf1eidh f65h rxb0dlc f45h txb0dlc f25h txb2dlc f05h rxf1sidl f64h rxb0eidl f44h txb0eidl f24h txb2eidl f04h rxf1sidh f63h rxb0eidh f43h txb0eidh f23h txb2eidh f03h rxf0eidh f62h rxb0sidl f42h txb0sidl f22h txb2sidl f02h rxf0eidl f61h rxb0sidh f41h txb0sidh f21h txb2sidh f01h rxf0sidl f60h rxb0con f40h txb0con f20h txb2con f00h rxf0sidh pic18cxx8 ds30475a-page 210 advanced information ? 2000 microchip technology inc. 17.3 can modes of o peration the pic18cxx8 has the following modes of operation. these modes are: configuration mode disable mode normal operation mode listen only mode loopback mode error recognition mode (selected through canrxm bits) modes are requested by setting the reqop bits, except the error recognition mode, which is requested through the canrxm bits. entry into a mode is acknowledged by monitoring the opmode bits. when changing modes, the mode will not actually change until all pending message transmissions are complete. because of this, the user must verify that the device has actually changed into the requested mode before further operations are executed. 17.3.1 configuration mode the can module has to be initialized before the activa- tion. this is only possible if the module is in the config- uration mode. the configuration mode is requested by setting reqop2 bit. only when the status bit opmode2 has a high level, the initialization can be performed. afterwards, the configuration registers and the acceptance mask registers and the acceptance fil- ter registers can be written. the module is activated by setting the control bits cfgreq to zero. the module will protect the user from accidentally vio- lating the can protocol through programming errors. all registers which control the configuration of the mod- ule can not be modified while the module is on-line. the can module will not be allowed to enter the con- figuration mode while a transmission is taking place. the config bit serves as a lock to protect the follow- ing registers. configuration registers bus timing registers identifier acceptance filter registers identifier acceptance mask registers in the configuration mode, the module will not transmit or receive. the error counters are cleared and the inter- rupt flags remain unchanged. the programmer will have access to configuration registers that are access restricted in other modes. 17.3.2 disable mode in disable mode, the module will not transmit or receive. the module has the ability to set the wakif bit due to bus activity, however, any pending interrupts will remain and the error counters will retain their value. if reqop<2:0> is set to 001 , the module will enter the module disable mode. this mode is similar to dis- abling other peripheral modules by turning off the mod- ule enables. this causes the module internal clock to stop unless the module is active (i.e., receiving or transmitting a message). if the module is active, the module will wait for 11 recessive bits on the can bus, detect that condition as an idle bus, then accept the module disable command. opmode<2:0>= 001 indi- cates whether the module successfully went into mod- ule disable mode the wakif interrupt is the only module interrupt that is still active in the module disable mode. if the wakie is set, the processor will receive an interrupt whenever the can bus detects a dominant state, as occurs with a sof. the i/o pins will revert to normal i/o function when the module is in the module disable mode. 17.3.3 normal mode this is the standard operating mode of the pic18cxx8. in this mode, the device actively monitors all bus messages and generates acknowledge bits, error frames, etc. this is also the only mode in which the pic18cxx8 will transmit messages over the can bus. 17.3.4 listen only mode listen only mode provides a means for the pic18cxx8 to receive all messages, including mes- sages with errors. this mode can be used for bus mon- itor applications, or for detecting the baud rate in ? hot plugging ? situations. for auto-baud detection, it is nec- essary that there are at least two other nodes which are communicating with each other. the baud rate can be detected empirically by testing different values until valid messages are received. the listen only mode is a silent mode, meaning no messages will be transmit- ted while in this state, including error flags or acknowl- edge signals. the filters and masks can be used to allow only particular messages to be loaded into the receive registers, or the filter masks can be set to all zeros to allow a message with any identifier to pass. the error counters are reset and deactivated in this state. the listen only mode is activated by setting the mode request bits in the cancon register. ? 2000 microchip technology inc. advanced information ds30475a-page 211 pic18cxx8 17.3.5 loopback mode this mode will allow internal transmission of messages from the transmit buffers to the receive buffers, without actually transmitting messages on the can bus. this mode can be used in system development and testing. in this mode, the ack bit is ignored and the device will allow incoming messages from itself just as if they were coming from another node. the loopback mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or acknowledge signals. the txcan pin will revert to port i/o while the device is in this mode. the filters and masks can be used to allow only particular messages to be loaded into the receive registers. the masks can be set to all zeros to provide a mode that accepts all messages. the loop- back mode is activated by setting the mode request bits in the cancon register. 17.3.6 error recognition mode the module can be set to ignore all errors and receive any message. the error recognition mode is activated by setting the rxm<1:0> bits in the rxbncon regis- ters to 11 . in this mode, the data which is in the mes- sage assembly buffer until the error time, is copied in the receive buffer and can be read via the cpu inter- face. in addition, the data which was on the internal sampling of the can bus at the error time and the state vector of the protocol state machine and the bit counter cntcan, are stored in registers and can be read. 17.4 can message transmission 17.4.1 transmit buffers the pic18cxx8 implements three transmit buffers. each of these buffers occupies 14 bytes of sram and are mapped into the device memory maps. for the mcu to have write access to the message buffer, the txreq bit must be clear, indicating that the message buffer is clear of any pending message to be transmitted. at a minimum, the txb n sidh, txb n sidl, and txb n dlc registers must be loaded. if data bytes are present in the message, the txb n dm registers must also be loaded. if the message is to use extended identifiers, the txb n eidm registers must also be loaded and the exide bit set. prior to sending the message, the mcu must initialize the txi n e bit to enable or disable the generation of an interrupt when the message is sent. the mcu must also initialize the txp priority bits (see section 17.4.2). 17.4.2 transmit priority transmit priority is a prioritization, within the pic18cxx8, of the pending transmittable messages. this is indepen- dent from, and not related to, any prioritization implicit in the message arbitration scheme built into the can proto- col. prior to sending the sof, the priority of all buffers that are queued for transmission is compared. the transmit buffer with the highest priority will be sent first. if two buff- ers have the same priority setting, the buffer with the highest buffer number will be sent first. there are four lev- els of transmit priority. if txp bits for a particular message buffer are set to 11 , that buffer has the highest possible priority. if txp bits for a particular message buffer are 00 , that buffer has the lowest possible priority. 17.4.3 initiating transmission to initiate message transmission, the txreq bit must be set for each buffer to be transmitted. when txreq is set, the txabt, txlarb and txerr bits will be cleared. setting the txreq bit does not initiate a message transmission, it merely flags a message buffer as ready for transmission. transmission will start when the device detects that the bus is available. the device will then begin transmission of the highest priority message that is ready. when the transmission has completed successfully, the txreq bit will be cleared, the txbnif bit will be set, and an interrupt will be generated if the txbnie bit is set. if the message transmission fails, the txreq will remain set indicating that the message is still pending for trans- mission and one of the following condition flags will be set. if the message started to transmit but encountered an error condition, the txerr and the irxif bits will be set and an interrupt will be generated. if the message lost arbitration, the txlarb bit will be set. 17.4.4 aborting transmission the mcu can request to abort a message by clearing the txbncon.txreq bit associated with the corre- sponding message buffer. setting cancon.abat bit will request an abort of all pending messages. if the message has not yet started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. the abort is indicated when the module sets txbncon.abtf bits. if the message has started to transmit, it will attempt to transmit the current message fully. if the current mes- sage is transmitted fully and is not lost to arbitration or an error, the abtf bit will not be set, because the mes- sage was transmitted successfully. likewise, if a mes- sage is being transmitted during an abort request and the message is lost to arbitration or an error, the mes- sage will not be re-transmitted and the abtf bit will be set, indicating that the message was successfully aborted. pic18cxx8 ds30475a-page 212 advanced information ? 2000 microchip technology inc. figure 17-2: transmit message flowchart start is can bus available to start transmission no examine txpri <1:0> to are any txreq ? bits = 1 the message transmission sequence begins when the device determines that the txreq for any of the transmit registers has been set. clear: txabt, txlarb, and txerr yes ? is txreq = 0 abat = 1 clearing the txreq bit while it is set, or setting the abat bit before the message has started transmission will abort the message. no begin transmission (sof) abort transmission: was message transmitted successfully? no yes set txreq = 0 is txie = 1? generate interrupt yes yes set txabt = 1 set set txerr = 1 yes no determine highest priority message no ? is txlarb = 1? the txie bit determines if an inter- rupt should be generated when a message is successfully transmitted. end is txreq = 0 or txabt = 1 ? yes no txbufe = 1 yes a message can also be aborted if a message error or lost arbitration condition occurred during transmission. arbitration lost during transmission ? 2000 microchip technology inc. advanced information ds30475a-page 213 pic18cxx8 17.5 message reception 17.5.1 receive message buffering the pic18cxx8 includes two full receive buffers with multiple acceptance filters for each. there is also a separate message assembly buffer (mab), which acts as a third receive buffer (see figure 17-3). 17.5.2 receive buffers of the three receive buffers, the mab is always commit- ted to receiving the next message from the bus. the remaining two receive buffers are called rxb0 and rxb1 and can receive a complete message from the protocol engine. the mcu can access one buffer while the other buffer is available for message reception, or holding a previously received message. the mab assembles all messages received. these messages will be transferred to the rxb n buffers, only if the acceptance filter criteria are met. when a message is moved into either of the receive buffers, the appropriate rxbnif bit is set. this bit must be cleared by the mcu when it has completed process- ing the message in the buffer, in order to allow a new message to be received into the buffer. this bit pro- vides a positive lockout to ensure that the mcu has fin- ished with the message before the pic18cxx8 attempts to load a new message into the receive buffer. if the rxbnie bit is set, an interrupt will be generated to indicate that a valid message has been received. 17.5.3 receive priority rxb0 is the higher priority buffer and has two message acceptance filters associated with it. rxb1 is the lower priority buffer and has four acceptance filters associ- ated with it. the lower number of acceptance filters makes the match on rxb0 more restrictive and implies a higher priority for that buffer. additionally, the rxb0con register can be configured such that if rxb0 contains a valid message, and another valid message is received, an overflow error will not occur and the new message will be moved into rxb1, regardless of the acceptance criteria of rxb1. there are also two programmable acceptance filter masks available, one for each receive buffer (see section 4.5). when a message is received, bits <3:0> of the rxb n con register will indicate the acceptance filter number that enabled reception, and whether the received message is a remote transfer request. the rxm bits set special receive modes. normally, these bits are set to 00 to enable reception of all valid messages, as determined by the appropriate accep- tance filters. in this case, the determination of whether or not to receive standard or extended messages is determined by the exide bit in the acceptance filter register. if the rxm bits are set to 01 or 10 , the receiver will accept only messages with standard or extended identifiers, respectively. if an acceptance filter has the exide bit set such that it does not correspond with the rxm mode, that acceptance filter is rendered useless. these two modes of rxm bits can be used in systems where it is known that only standard or extended mes- sages will be on the bus. if the rxm bits are set to 11 , the buffer will receive all messages, regardless of the values of the acceptance filters. also, if a message has an error before the end of frame, that portion of the message assembled in the mab before the error frame, will be loaded into the buffer. this mode has some value in debugging a can system and would not be used in an actual system environment. note: the entire contents of the mab is moved into the receive buffer once a message is accepted. this means that regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is overwritten with the mab contents. therefore, the contents of all regis- ters in the buffer must be assumed to have been modified when any message is received. pic18cxx8 ds30475a-page 214 advanced information ? 2000 microchip technology inc. figure 17-3: receive buffer block diagram acceptance mask rxm1 acceptance filter rxf2 acceptance filter rxf3 acceptance filter rxf4 acceptance filter rxf5 acceptance mask rxm0 acceptance filter rxf0 acceptance filter rxf1 identifier data field data field identifier a c c e p t a c c e p t r x b 0 r x b 1 m a b ? 2000 microchip technology inc. advanced information ds30475a-page 215 pic18cxx8 figure 17-4: message reception flowchart start detect start of message? valid message received? generate error message identifier meets a filter criteria? is rxrdy = 0? go to start move message into rxb0 set rxrdy = 1 set filhit <2:0> is rxrdy = 0? move message into rxb1 set rxrdy = 1 yes, meets criteria for rxbo yes, meets criteria for rxb1 no generate interrupt yes ye s no no yes ye s no no yes yes frame the rxrdy bit determines if the receive register is empty and able to accept a new message. no ye s no generate overrun error: begin loading message into message assembly buffer (mab) according to which filter criteria was met is rxie = 1? is rxie = 1? is rx0dben = 1? the rxb0dben bit determines if rxb0 can roll over into rxb1 if it is full. set rxb0ovfl generate overrun error: set rxb1ovfl is errie = 1? no go to start ye s no set filhit <0> according to which filter criteria was met set canstat <3:0> according to which receive buffer the message was loaded into pic18cxx8 ds30475a-page 216 advanced information ? 2000 microchip technology inc. 17.6 message acceptance filters and m asks the message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buff- ers. once a valid message has been received into the mab, the identifier fields of the message are compared to the filter values. if there is a match, that message will be loaded into the appropriate receive buffer. the filter masks are used to determine which bits in the identifier are examined with the filters. a truth table is shown below in table 17-2 that indicates how each bit in the identifier is compared to the masks and filters to deter- mine if a the message should be loaded into a receive buffer. the mask essentially determines which bits to apply the acceptance filters to. if any mask bit is set to a zero, then that bit will automatically be accepted, regardless of the filter bit. table 17-2: filter/mask truth table as shown in the receive buffers block diagram (figure 17-3), acceptance filters rxf0 and rxf1, and filter mask rxm0 are associated with rxb0. filters rxf2, rxf3, rxf4, and rxf5 and mask rxm1 are associated with rxb1. when a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the filhit bit(s). for rxb1, the rxb1con regis- ter contains the filhit<2:0> bits. they are coded as follows: 101 = acceptance filter 5 (rxf5) 100 = acceptance filter 4 (rxf4) 011 = acceptance filter 3 (rxf3) 010 = acceptance filter 2 (rxf2) 001 = acceptance filter 1 (rxf1) 000 = acceptance filter 0 (rxf0) the coding of the rxb0dben bit enables these three bits to be used similarly to the filhit bits and to distin- guish a hit on filter rxf0 and rxf1, in either rxb0, or after a roll over into rxb1. 111 = acceptance filter 1 (rxf1) 110 = acceptance filter 0 (rxf0) 001 = acceptance filter 1 (rxf1) 000 = acceptance filter 0 if the rxb0dben bit is clear, there are six codes cor- responding to the six filters. if the rxb0dben bit is set, there are six codes corresponding to the six filters, plus two additional codes corresponding to rxf0 and rxf1 filters that roll over into rxb1. if more than one acceptance filter matches, the filhit bits will encode the binary value of the lowest num- bered filter that matched. in other words, if filter rxf2 and filter rxf4 match, filhit will be loaded with the value for rxf2. this essentially prioritizes the accep- tance filters with a lower number filter having higher pri- ority. messages are compared to filters in ascending order of filter number. the mask and filter registers can only be modified when the pic18cxx8 is in configuration mode. the mask and filter registers cannot be read outside of con- figuration mode. when outside of configuration mode, all mask and filter registers will be read as ? 0 ? . mask bit n filter bit n message identifier bit n001 accept or reject bit n 0 x x accept 1 0 0 accept 1 0 1 reject 1 1 0 reject 1 1 1 accept legend: x = don ? t care note: 000 and 001 can only occur if the rxb0dben bit is set in the rxb0con register, allowing rxb0 messages to roll over into rxb1. ? 2000 microchip technology inc. advanced information ds30475a-page 217 pic18cxx8 figure 17-5: message acceptance mask and filter operation acceptance filter register acceptance mask register rxrqst message assembly buffer rxfn 0 rxfn 1 rxfn n rxmn 0 rxmn 1 rxmn n identifier pic18cxx8 ds30475a-page 218 advanced information ? 2000 microchip technology inc. 17.7 baud ra te setting all nodes on a given can bus must have the same nominal bit rate. the can protocol uses non-return-to-zero (nrz) coding, which does not encode a clock within the data stream. therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitters clock. as oscillators and transmission time may vary from node to node, the receiver must have some type of phase lock loop (pll) synchronized to data transmis- sion edges, to synchronize and maintain the receiver clock. since the data is nrz coded, it is necessary to include bit stuffing to ensure that an edge occurs at least every six bit times, to maintain the digital phase lock loop (dpll) synchronization. the bit timing of the pic18cxx8 is implemented using a dpll that is configured to synchronize to the incom- ing data, and provide the nominal timing for the trans- mitted data. the dpll breaks each bit time into multiple segments, made up of minimal periods of time called the time quanta (t q ). bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network transmission delay compensation, and sample point positioning, are defined by the programmable bit timing logic of the dpll. all devices on the can bus must use the same bit rate. however, all devices are not required to have the same master oscillator clock frequency. for the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each seg- ment. the nominal bit rate is the number of bits transmitted per second assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. the nominal bit rate is defined to be a maximum of 1mb/s. nominal bit time is defined as: t bit = 1 / nomlnal blt rate the nominal bit time can be thought of as being divided into separate non-overlapping time segments. these segments are shown in figure 17-6. synchronization segment (sync_seg) propagation time segment (prop_seg) phase buffer segment 1 (phase_seg1) phase buffer segment 2 [phase_seg2) nominal bit time = t q * (sync_seg + prop_seg + phase_seg1 + phase_seg2) the time segments and also, the nominal bit time, are made up of integer units of time called time quanta or t q (see figure 17-6). by definition, the nominal bit time is programmable from a minimum of 8 t q to a maxi- mum of 25 t q . also by definition, the minimum nominal bit time is 1 s, corresponding to a maximum 1 mb/s rate. figure 17-6: bit time partitioning input signal sync prop segment phase segment 1 phase segment 2 sample point t q ? 2000 microchip technology inc. advanced information ds30475a-page 219 pic18cxx8 17.7.1 time quanta the time quanta is a fixed unit of time derived from the oscillator period. there is a programmable baud rate prescaler, with integral values ranging from 1 to 64, in addition to a fixed divide by two for clock generation. example 17-2: calculation for f osc = 16mhz example 17-3: calculation for f osc = 20mhz example 17-4: calculation for f osc = 25mhz the frequencies of the oscillators in the different nodes must be coordinated in order to provide a system-wide specified nominal bit time. this means that all oscilla- tors must have a t osc that is a integral divisor of t q . it should also be noted that although the number of t q is programmable from 4 to 25, the usable minimum is 8t q . a bit time of less than 8 t q in length is not guar- anteed to operate correctly. 17.7.2 synchronization segment this part of the bit time is used to synchronize the var- ious can nodes on the bus. the edge of the input sig- nal is expected to occur during the sync segment. the duration is 1 t q . 17.7.3 propagation segment this part of the bit time is used to compensate for phys- ical delay times within the network. these delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. the length of the propagation segment can be programmed from 1t q to 8 t q by setting the prseg2:prseg0 bits. 17.7.4 phase buffer segments the phase buffer segments are used to optimally locate the sampling point of the received bit, within the nominal bit time. the sampling point occurs between phase seg- ment 1 and phase segment 2. these segments can be lengthened or shortened by the resynchronization pro- cess. the end of phase segment 1 determines the sam- pling point within a bit time. phase segment 1 is programmable from 1 t q to 8 t q in duration. phase seg- ment 2 provides delay before the next transmitted data transition and is also programmable from 1 t q to 8 t q in duration (however, due to ipt requirements the actual minimum length of phase segment 2 is 2 t q , or it may be defined to be equal to the greater of phase segment 1 or the information processing time (ipt) ). 17.7.5 sample point the sample point is the point of time at which the bus level is read and value of the received bit is determined. the sampling point occurs at the end of phase segment 1. if the bit timing is slow and contains many t q , it is possible to specify multiple sampling of the bus line at the sample point. the value of the received bit is determined to be the value of the majority decision of three values. the three samples are taken at the sam- ple point, and twice before with a time of t q /2 between each sample. 17.7.6 information processing time the information processing time (ipt) is the time seg- ment, starting at the sample point, that is reserved for calculation of the subsequent bit level. the can speci- fication defines this time to be less than or equal to 2 t q . the pic18cxx8 defines this time to be 2 t q . thus, phase segment 2 must be at least 2 t q long. if fosc = 16 mhz, brp<5:0> = 00h, and nominal bit time = 8 t q ; then t q = 125 nsec and nominal bit rate = 1 mb/s if f osc = 20 mhz, brp<5:0> = 01h, and nominal bit time = 8 t q ; then t q = 200nsec and nominal bit rate = 625 kb/s if fosc = 25 mhz, brp<5:0> = 3fh, and nominal bit time = 25 t q ; then t q = 5.12 usec and nominal bit rate = 7.8 kb/s pic18cxx8 ds30475a-page 220 advanced information ? 2000 microchip technology inc. 17.8 synchronization to compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each can controller must be able to synchronize to the relevant signal edge of the incoming signal. when an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (sync seg). the circuit will then adjust the values of phase segment 1 and phase segment 2, as necessary. there are two mechanisms used for synchronization. 17.8.1 hard synchronization hard synchronization is only done when there is a recessive to dominant edge during a bus idle condi- tion, indicating the start of a message. after hard syn- chronization, the bit time counters are restarted with sync seg. hard synchronization forces the edge, which has occurred to lie within the synchronization segment of the restarted bit time. due to the rules of synchroni- zation, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 17.8.2 resynchronization as a result of resynchronization, phase segment 1 may be lengthened, or phase segment 2 may be short- ened. the amount of lengthening or shortening of the phase buffer segments has an upper bound given by the synchronization jump width (sjw). the value of the sjw will be added to phase segment 1 (see figure 17-7), or subtracted from phase segment 2 (see figure 17-8). the sjw is programmable between 1 t q and 4 t q . clocking information will only be derived from reces- sive to dominant transitions. the property that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. the phase error of an edge is given by the position of the edge relative to sync seg, measured in t q . the phase error is defined in magnitude of t q as follows: e = 0 if the edge lies within synceseg. e > 0 if the edge lies before the sample point. e < 0 if the edge lies after the sample point of the previous bit. if the magnitude of the phase error is less than, or equal to, the programmed value of the synchronization jump width, the effect of a resynchronization is the same as that of a hard synchronization. if the magnitude of the phase error is larger than the synchronization jump width, and if the phase error is positive, then phase segment 1 is lengthened by an amount equal to the synchronization jump width. if the magnitude of the phase error is larger than the resynchronization jump width, and if the phase error is negative, then phase segment 2 is shortened by an amount equal to the synchronization jump width. 17.8.3 synchronization rules only one synchronization within one bit time is allowed. an edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge. all other recessive to dominant edges, fulfilling rules 1 and 2, will be used for resynchronization with the exception that a node transmitting a dom- inant bit will not perform a resynchronization, as a result of a recessive to dominant edge with a pos- itive phase error. ? 2000 microchip technology inc. advanced information ds30475a-page 221 pic18cxx8 figure 17-7: lengthening a bit period figure 17-8: shortening a bit period input signal sync prop segment phase segment 1 phase segment 2 sjw sample nominal actual bit length bit length point t q input signal sync prop segment phase segment 1 phase segment 2 sjw sample actual nominal bit length t q point bit length pic18cxx8 ds30475a-page 222 advanced information ? 2000 microchip technology inc. 17.9 programming time segments some requirements for programming of the time segments: prop seg + phase seg 1 phase seg 2 phase seg 2 sync jump width for example, assuming that a 125 khz can baud rate with f osc = 20 mhz is desired: t osc = 50nsec, choose brp<5:0> = 04h, then t q = 500nsec. to obtain 125 khz, the bit time must be 16 t q . sync seg = 1 t q ; prop seg = 2 t q ; so, setting phase seg 1 = 7 t q would place the sample at 10 t q after the transition. this would leave 6 t q for phase seg 2. since phase seg 2 is 6, by the rules, sjw could be the maximum of 4 t q . however, normally a large sjw is only necessary when the clock generation of the differ- ent nodes is inaccurate or unstable, such as using ceramic resonators. so an sjw of 1 is typically enough. 17.10 oscillator tolerance the bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 kbit/sec, as a rule of thumb. for the full bus speed range of the can protocol, a quartz oscillator is required. a maximum node-to-node oscillator variation of 1.7% is allowed. 17.11 bit timing configuration registers the configuration registers (brgcon1, brgcon2, brgcon3) control the bit timing for the can bus inter- face. these registers can only be modified when the pic18cxx8 is in configuration mode. 17.11.1 brgcon1 the brp bits control the baud rate prescaler. the sjw<1:0> bits select the synchronization jump width in terms of number of t q ? s. 17.11.2 brgcon2 the prseg bits set the length, in t q ? s, of the propaga- tion segment. the seg1ph bits set the length, in t q ? s, of phase segment 1. the sam bit controls how many times the rxcan pin is sampled. setting this bit to a ? 1 ? causes the bus to be sampled three times; twice at t q /2 before the sample point, and once at the normal sample point (which is at the end of phase segment 1). the value of the bus is determined to be the value read during at least two of the samples. if the sam bit is set to a ? 0 ? , then the rxcan pin is sampled only once at the sample point. the seg2phts bit controls how the length of phase segment 2 is determined. if this bit is set to a ? 1 ? , then the length of phase segment 2 is deter- mined by the seg2ph bits of brgcon3. if the seg2phts bit is set to a ? 0 ? , then the length of phase segment 2 is the greater of phase segment 1 and the information processing time (which is fixed at 2 t q for the pic18cxx8). 17.11.3 brgcon3 the phseg2<2:0> bits set the length, in t q ? s, of phase segment 2, if the seg2phts bit is set to a ? 1 ? . if the seg2phts bit is set to a ? 0 ? , then the phseg2<2:0> bits have no effect. ? 2000 microchip technology inc. advanced information ds30475a-page 223 pic18cxx8 17.12 error detection the can protocol provides sophisticated error detec- tion mechanisms. the following errors can be detected. 17.12.1 crc error with the cyclic redundancy check (crc), the trans- mitter calculates special check bits for the bit sequence, from the start of a frame until the end of the data field. this crc sequence is transmitted in the crc field. the receiving node also calculates the crc sequence using the same formula and performs a comparison to the received sequence. if a mismatch is detected, a crc error has occurred and an error frame is generated. the message is repeated. 17.12.2 acknowledge error in the acknowledge field of a message, the transmitter checks if the acknowledge slot (which has sent out as a recessive bit) contains a dominant bit. if not, no other node has received the frame correctly. an acknowl- edge error has occurred; an error frame is generated and the message will have to be repeated. 17.12.3 form error lf a node detects a dominant bit in one of the four seg- ments, including end of frame, interframe space, acknowledge delimiter, or crc delimiter, then a form error has occurred and an error frame is generated. the message is repeated. 17.12.4 bit error a bit error occurs if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual bus level and comparing it to the just transmitted bit. in the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the acknowledge slot, no bit error is generated because normal arbitration is occurring. 17.12.5 stuff bit error lf, between the start of frame and the crc delimiter, six consecutive bits with the same polarity are detected, the bit stuffing rule has been violated. a stuff bit error occurs and an error frame is generated. the message is repeated. 17.12.6 error states detected errors are made public to all other nodes via error frames. the transmission of the erroneous mes- sage is aborted and the frame is repeated as soon as possible. furthermore, each can node is in one of the three error states ? error-active ? , ? error-passive ? or ? bus-off ? according to the value of the internal error counters. the error-active state is the usual state, where the bus node can transmit messages and active error frames (made of dominant bits), without any restrictions. in the error-passive state, messages and passive error frames (made of recessive bits) may be transmitted. the bus-off state makes it temporarily impossible for the station to participate in the bus com- munication. during this state, messages can neither be received nor transmitted. 17.12.7 error modes and error counters the pic18cxx8 contains two error counters: the receive error counter (rxerrcnt), and the trans- mit error counter (txerrcnt). the values of both counters can be read by the mcu. these counters are incremented or decremented in accordance with the can bus specification. the pic18cxx8 is error-active if both error counters are below the error-passive limit of 128. it is error-passive if at least one of the error counters equals or exceeds 128. it goes to bus-off if the transmit error counter equals or exceeds the bus-off limit of 256. the device remains in this state, until the bus-off recovery sequence is received. the bus-off recovery sequence consists of 128 occurrences of 11 consecutive reces- sive bits (see figure 17-9). note that the can module, after going bus-off, will recover back to error-active, without any intervention by the mcu, if the bus remains idle for 128 x 11 bit times. if this is not desired, the error interrupt service routine should address this. the cur- rent error mode of the can module can be read by the mcu via the comstat register. additionally, there is an error state warning flag bit, ewarn, which is set if at least one of the error counters equals or exceeds the error warning limit of 96. ewarn is reset if both error counters are less than the error warning limit. pic18cxx8 ds30475a-page 224 advanced information ? 2000 microchip technology inc. figure 17-9: error modes state diagram bus off error active error passive rxerrcnt < 127 or txerrcnt < 127 rxerrcnt > 127 or txerrcnt > 127 txerrcnt > 255 128 occurrences of 11 consecutive "recessive" bits reset ? 2000 microchip technology inc. advanced information ds30475a-page 225 pic18cxx8 17.13 can interrupts the module has several sources of interrupts. each of these interrupts can be individually enabled or dis- abled. the canintf register contains interrupt flags. the caninte register contains the enables for the 8 main interrupts. a special set of read only bits in the canstat register (icode bits) can be used in combi- nation with a jump table for efficient handling of inter- rupts. all interrupts have one source, with the exception of the error interrupt. any of the error interrupt sources can set the error interrupt flag. the source of the error interrupt can be determined by reading the communi- cation status register comstat. the interrupts can be broken up into two categories: receive and transmit interrupts. the receive related interrupts are: receive interrupts wake-up interrupt receiver overrun interrupt receiver warning interrupt receiver error passive interrupt the transmit related interrupts are transmit interrupts transmitter warning interrupt transmitter error passive interrupt bus off interrupt 17.13.1 interrupt code bits the source of a pending interrupt is indicated in the icode (interrupt code) bits. interrupts are internally prioritized, such that the lower the icode value, the higher the interrupt priority. once the highest priority interrupt condition has been cleared, the code for the next highest priority interrupt that is pending (if any), will be reflected by the icode bits (see table 17-3). note that only those interrupt sources that have their associated caninte enable bit set will be reflected in the icode bits. table 17-3: icode<2:0> decode 17.13.2 transmit interrupt when the transmit interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. the txbnif bit will be set to indicate the source of the interrupt. the interrupt is cleared by the mcu resetting the txbnif bit to a ? 0 ? . 17.13.3 receive interrupt when the receive interrupt is enabled, an interrupt will be generated when a message has been successfully received and loaded into the associated receive buffer. this interrupt is activated immediately after receiving the eof field. the rxbnif bit will be set to indicate the source of the interrupt. the interrupt is cleared by the mcu resetting the rxbnif bit to a ? 0 ? . 17.13.4 message error interrupt when an error occurs during transmission or reception of a message, the message error flag irxif will be set and, if the irxie bit is set, an interrupt will be gener- ated. this is intended to be used to facilitate baud rate determination when used in conjunction with listen only mode. 17.13.5 bus activity wake-up interrupt when the pic18cxx8 is in sleep mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated, and the wakif bit will be set, when activity is detected on the can bus. this interrupt causes the pic18cxx8 to exit sleep mode. the interrupt is reset by the mcu clearing the wakif bit. icode<2:0> boolean expression 000 err wak tx0 tx1 tx2 rx0 rx1 001 err 010 err wak 011 err wak tx0 100 err wak tx0 tx1 101 err wak tx0 tx1 tx2 110 err wak tx0 tx1 tx2 rx0 111 err wak tx0 tx1 tx2 rx0 rx1 pic18cxx8 ds30475a-page 226 advanced information ? 2000 microchip technology inc. 17.13.6 error interrupt when the error interrupt is enabled, an interrupt is gen- erated if an overflow condition occurs, or if the error state of transmitter or receiver has changed. the error flags in comstat will indicate one of the following conditions. 17.13.6.1 receiver overflow an overflow condition occurs when the mab has assem- bled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. the associated comstat.rx n ovfl bit will be set to indicate the overflow condition. this bit must be cleared by the mcu. 17.13.6.2 receiver warning the receive error counter has reached the mcu warn- ing limit of 96. 17.13.6.3 transmitter warning the transmit error counter has reached the mcu warn- ing limit of 96. 17.13.6.4 receiver bus-passive the receive error counter has exceeded the error-passive limit of 127 and the device has gone to error-passive state. 17.13.6.5 transmitter bus-passive the transmit error counter has exceeded the error- passive limit of 127 and the device has gone to error- passive state. 17.13.6.6 bus-off the transmit error counter has exceeded 255 and the device has gone to bus-off state. 17.13.7 interrupt acknowledge interrupts are directly associated with one or more sta- tus flags in the pif register. interrupts are pending as long as one of the flags is set. once an interrupt flag is set by the device, the flag can not be reset by the mcu until the interrupt condition is removed. ? 2000 microchip technology inc. advanced information ds30475a-page 227 pic18cxx8 18.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has twelve inputs for the pic18c658 devices and sixteen for the pic18c858 devices. this module has the adcon0, adcon1, and adcon2 registers. the a/d allows conversion of an analog input signal to a corresponding 10-bit digital number. the a/d module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 18-1, con- trols the operation of the a/d module. the adcon1 register, shown in register 18-2, configures the func- tions of the port pins. the adcon2, shown in register 16-3, configures the a/d clock source and justification. register 18-1: adcon0 register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 00, (an0) 0001 = channel 01, (an1) 0010 = channel 02, (an2) 0011 = channel 03, (an3) 0100 = channel 04, (an4) 0101 = channel 05, (an5) 0110 = channel 06, (an6) 0111 = channel 07, (an7) 1000 = channel 08, (an8) 1001 = channel 09, (an9) 1010 = channel 10, (an10) 1011 = channel 11, (an11) 1100 = channel 12, (an12) (1) 1101 = channel 13, (an13) (1) 1110 = channel 14, (an14) (1) 1111 = channel 15, (an15) (1) note 1: these channels are not available on the pic18c658 devices. bit 1 go/done : a/d conversion status bit when adon = 1 1 = a/d conversion in progress. setting this bit starts an a/d conversion cycle. this bit is auto- matically cleared by hardware when the a/d conversion is complete. 0 = a/d conversion not in progress bit 0 adon: a/d on bit 1 = a/d converter module is operating 0 = a/d converter module is shut off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 228 advanced information ? 2000 microchip technology inc. register 18-2: adcon1 register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5-4 vcfg1:vcfg0: voltage reference configuration bits bit 3:0 pcfg3:pcfg0: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown note: channels an15 through an12 are not available on the 68-pin devices. a/d v ref + a/d v ref - 00 a vdd a vss 01 external v ref +a vss 10 a vdd external v ref - 11 external v ref + external v ref - a = analog input d = digital i/o shaded cells = additional a/d channels available on the pic18c858 devices. an15 an14 an13 an12 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a a a a a aaaaaaaaaaa 0001 d d a a a aaaaaaaaaaa 0010 d d d a a aaaaaaaaaaa 0011 d d d d a aaaaaaaaaaa 0100 d d d dd aaaaaaaaaaa 0101 d d d dd daaaaaaaaaa 0110 d d d dd ddaaaaaaaaa 0111 d d d d d d d d a a a a aaaa 1000 d d d d d d d d d a a a aaaa 1001 d d d d d dddddaaaaaa 1010 d d d d d ddddddaaaaa 1011 d d d d d dddddddaaaa 1100 d d d d d ddddddddaaa 1101 d d d d d dddddddddaa 1110 d d d d d dddddddddda 1111 d d d d d ddddddddddd ? 2000 microchip technology inc. advanced information ds30475a-page 229 pic18cxx8 register 18-3: adcon2 register r/w-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 adfm ? ? ? ? adcs2 adcs1 adcs0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6-3 unimplemented: read as '0' bit 2-0 adcs1:adcs0: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 011 = f rc (clock derived from an rc oscillator = 1 mhz max) 100 = f osc /4 101 = f osc /16 110 = f osc /64 111 = f rc (clock derived from an rc oscillator = 1 mhz max) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 230 advanced information ? 2000 microchip technology inc. the analog reference voltage is software selectable to either the device ? s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/v ref + pin and ra2/an2/v ref -. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/d ? s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion is aborted. each port pin associated with the a/d converter can be configured as an analog input (ra3 can also be a voltage reference), or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is complete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared, and a/d interrupt flag bit adif is set. the block diagram of the a/d module is shown in figure 18-1. figure 18-1: a/d block diagram (input voltage) v ain v ref + reference voltage v dd vcfg1:vcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 10-bit converter v ref - v ss a/d an15 (1) an14 (1) an13 (1) an12 (1) an11 an10 an9 an8 1111 1110 1101 1100 1011 1010 1001 1000 note 1: channels an15 through an12 are not available on the pic18c658. 2: i/o pins have diode protection to v dd and v ss . ? 2000 microchip technology inc. advanced information ds30475a-page 231 pic18cxx8 the value in the adresh/adresl registers is not modified for a power-on reset. the adresh/adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 18.1. after this acquisition time has elapsed, the a/d conver- sion can be started. the following steps should be fol- lowed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2t ad is required before next acquisition starts. figure 18-2: analog input model v ain c pin rs anx 5 pf v dd v t = 0.6 v v t = 0.6 v i leakage r ic 1 k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 ( k ? ) v dd 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss pic18cxx8 ds30475a-page 232 advanced information ? 2000 microchip technology inc. 18.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 18-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5k ? . after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 18-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 18-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assump- tions: c hold = 120 pf rs = 2.5 k ? conversion error 1/2 lsb v dd = 5v rss = 7 k ? temperature = 50 c (system max.) v hold =0v @ time = 0 equation 18-1: acquisition time equation 18-2: a/d minimum charging time example 18-1: calculating the minimum required acquisition time note: when the conversion is started, the hold- ing capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref - (v ref /2048)) (1 - e (-tc/c hold (r ic + r ss + r s )) ) or tc = -(120 pf)(1 k ? + r ss + r s ) ln(1/2047) t acq =t amp + t c + t coff temperature coefficient is only required for temperatures > 25 c. t acq =2 s + tc + [( tem p - 2 5 c)(0.05 s/ c)] t c =-c hold (r ic + r ss + r s ) ln(1/2047) -120 pf (1 k ? + 7 k ? + 2.5 k ? ) ln(0.0004885) -120 pf (10.5 k ? ) ln(0.0004885) -1.26 s (-7.6241) 9.61 s t acq =2 s + 9.61 s + [(50 c - 25 c)(0.05 s/ c)] 11.61 s + 1.25 s 12.86 s ? 2000 microchip technology inc. advanced information ds30475a-page 233 pic18cxx8 18.2 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 12 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2t osc 4t osc 8t osc 16t osc 32t osc 64t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be selected to ensure a minimum t ad time of 1.6 s. table 18-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. 18.3 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (out- put), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. table 18-1: t ad vs. device operating frequencies note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will not affect the conver- sion accuracy. 2: analog levels on any pin defined as a dig- ital input may cause the input buffer to consume current out of the device ? s spec- ification limits. ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 pic18cxx8 pic18lcxx8 (6) 2t osc 000 1.25 mhz 666 khz 4t osc 100 2.50 mhz 1.33 mhz 8t osc 001 5.00 mhz 2.67 mhz 16t osc 101 10.0 mhz 5.33 mhz 32t osc 010 20.0 mhz 10.67 mhz 64t osc 110 40.0 mhz 21.33 mhz rc x11 ?? note 1: the rc source has a typical t ad time of 4 ms. 2: the rc source has a typical t ad time of 6 ms. 3: these values violate the minimum required t ad time. 4: for faster conversion times, the selection of another clock source is recommended. 5: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or the a/d accuracy may be out of specification. 6: this column is for the lc devices only. pic18cxx8 ds30475a-page 234 advanced information ? 2000 microchip technology inc. 18.4 a /d conversions figure 18-3 shows the operation of the a/d converter after the go bit has been set. clearing the go/done bit during a conversion will abort the current conver- sion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. that is, the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl reg- isters). after the a/d conversion is aborted, a 2t ad wait is required before the next acquisition is started. after this 2t ad wait, acquisition on the selected channel is automatically started. 18.5 use of the ccp2 trigger an a/d conversion can be started by the ? special event trigger ? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as 1011 and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ? special event trigger ? sets the go/done bit (starts a conver- sion). if the a/d module is not enabled (adon is cleared), the ? special event trigger ? will be ignored by the a/d mod- ule, but will still reset the timer1 (or timer3) counter. figure 18-3: a/d conversion t ad cycles note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 9 t ad 10 b1 b0 tc y - t ad next q4: adresh/adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 ? 2000 microchip technology inc. advanced information ds30475a-page 235 pic18cxx8 table 18-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 0000 0000 0000 0000 pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip -0-- 0000 -0-- 0000 adresh a/d result register xxxx xxxx uuuu uuuu adresl a/d result register xxxx xxxx uuuu uuuu adcon0 ? ? chs3 chs3 chs1 chs0 go/done adon 0000 00-0 0000 00-0 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 ---- -000 ---- -000 adcon2 adfm ? ? ? ? adcs2 adcs1 adcs0 0--- -000 0--- -000 porta ? ra6 ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 trisa ? porta data direction register --11 1111 --11 1111 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 x000 0000 u000 0000 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx xxxx uuuu uuuu trisf portf data direction control register 1111 1111 1111 1111 porth (1) rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 0000 xxxx 0000 xxxx lath (1) lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 xxxx xxxx uuuu uuuu trish (1) porth data direction control register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. shaded cells are not used for a/d conversion. note 1: only available on pic18c858 devices. pic18cxx8 ds30475a-page 236 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 237 pic18cxx8 19.0 comparator module the comparator module contains two analog compara- tors. the inputs to the comparators are multiplexed with the rf1 through rf6 pins. the on-chip voltage reference (section 20.0) can also be an input to the comparators. the cmcon register, shown as register 19-1, con- trols the comparator input and output multiplexers. a block diagram of the comparator is shown in figure 19-1. register 19-1: cmcon register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output when c2inv = 0: 1 = c2 v in + > c2 v in ? 0 = c2 v in + < c2 v in ? when c2inv = 1 : 1 = c2 v in + < c2 v in ? 0 = c2 v in + > c2 v in ? bit 6 c1out : comparator 1 output when c1inv = 0: 1 = c1 v in + > c1 v in ? 0 = c1 v in + < c1 v in ? when c1inv = 1 : 1 = c1 v in + < c1 v in ? 0 = c1 v in + > c1 v in ? bit 5 c2inv : comparator 2 output inversion 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch when cm2:cm0 = 110 : 1 = c1 v in ? connects to rf5/an10 c2 v in ? connects to rf3/an8 0 = c1 v in ? connects to rf6/an11 c2 v in ? connects to rf4/an9 bit 2-0 cm2:cm0 : comparator mode figure 19-1 shows the comparator modes and cm2:cm0 bit settings legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 238 advanced information ? 2000 microchip technology inc. 19.1 comparator configuration there are eight modes of operation for the compara- tors. the cmcon register is used to select these modes. figure 19-1 shows the eight possible modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in electrical specifications (section 25.0). figure 19-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change. other- wise, a false interrupt may occur. c1 rf6/an11 v in - v in + rf5/an10 off (read as ? 0 ? ) comparators reset (por default value) a a cm2:cm0 = 000 c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ? ) a a c1 rf6/an11 v in - v in + rf5/an10 c1out two independent comparators a a cm2:cm0 = 010 c2 rf4/an9 v in - v in + rf3/an8 c2out a a c1 rf6/an11 v in - v in + rf5/an10 c1out two common reference comparators a a cm2:cm0 = 100 c2 rf4/an9 v in - v in + rf3/an8 c2out a d c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ? ) one independent comparator with output d d cm2:cm0 = 001 c1 rf6/an11 v in - v in + rf5/an10 c1out a a c1 rf6/an11 v in - v in + rf5/an10 off (read as ? 0 ? ) comparators off d d cm2:cm0 = 111 c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ? ) d d c1 rf6/an11 v in - v in + rf5/an10 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 rf4/an9 v in - v in + rf3/an8 c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 rf6/an11 v in - v in + rf5/an10 c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 rf4/an9 v in - v in + rf3/an8 c2out a d a = analog input, port reads zeros always. d = digital input. cis (cmcon<3>) is the comparator input switch. cv ref c1 rf6/an11 v in - v in + rf5/an10 c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 rf4/an9 v in - v in + rf3/an8 c2out a a rf2/an7/c1out rf1/an6/c2out rf2/an7/c1out rf1/an6/c2out rf2/an7/c1out ? 2000 microchip technology inc. advanced information ds30475a-page 239 pic18cxx8 19.2 comparator operation a single comparator is shown in figure 19-2 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in ? , the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in ? , the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 19-2 represent the uncertainty due to input offsets and response time. 19.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in ? is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly (figure 19-2). figure 19-2: single comparator 19.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same, or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd , and can be applied to either pin of the comparator(s). 19.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. section 20.0 contains a detailed descrip- tion of the comparator voltage reference module that provides this signal. the internal reference signal is used when comparators are in mode cm<2:0> = 110 (figure 19-1). in this mode, the internal voltage refer- ence is applied to the v in + pin of both comparators. 19.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise the maximum delay of the comparators should be used (section 25.0). 19.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf1 and rf2 i/o pins. when enabled, multiplexors in the output path of the rf1 and rf2 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 19-3 shows the comparator output block diagram. the trisa bits will still function as an output enable/disable for the rf1 and rf2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). ? + v in + v in ? output v in ? v in+ utput output v in + v in ? note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ? . pins configured as digital inputs will convert an analog input, according to the schmitt trigger input specification. 2: analog levels on any pin defined as a dig- ital input, may cause the input buffer to consume more current than is specified. pic18cxx8 ds30475a-page 240 advanced information ? 2000 microchip technology inc. figure 19-3: comparator output block diagram d q en to rf1 or rf2 pin bus data read cmcon set multiplex cmif bit - + d q en cl port pins read cmcon r eset from other comparator cxinv ? 2000 microchip technology inc. advanced information ds30475a-page 241 pic18cxx8 19.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir registers) is the comparator interrupt flag. the cmif bit must be reset by clearing ? 0 ? . since it is also possible to write a '1' to this register, a simulated inter- rupt may be initiated. the cmie bit (pie registers) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. . the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mis- match condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition, and allow flag bit cmif to be cleared. 19.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from sleep mode, when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current, as shown in the com- parator specifications. to minimize power consumption while in sleep mode, turn off the comparators, cm<2:0> = 111 , before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 19.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator reset mode, cm<2:0> = 000 . this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators will be powered down during the reset interval. note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir regis- ters) interrupt flag may not get set. pic18cxx8 ds30475a-page 242 advanced information ? 2000 microchip technology inc. 19.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 19-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6 v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is rec- ommended for the analog sources. any external com- ponent connected to an analog input pin, such as a capacitor or a zener diode, should have very little leak- age current. figure 19-4: analog input model table 19-1: registers associated with comparator module va r s < 10k a in c pin 5 pf v dd v t = 0.6 v v t = 0.6 v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 vrcon vren vroe vrr vrss vr3 vr2 vr1 vr0 0000 0000 0000 0000 intcon gie/ gieh peie/ giel tmr0ie intie rbie tmr0if intif rbif 0000 000x 0000 000u pir2 ? cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ? cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr2 ? cmip ? ? bclip lvdip tmr3ip ccp2ip -1-- 1111 -1-- 1111 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 x000 0000 u000 0000 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx xxxx uuuu uuuu trisf portf data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as "0" ? 2000 microchip technology inc. advanced information ds30475a-page 243 pic18cxx8 20.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage refer- ence. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down func- tion to conserve power when the reference is not being used. the cvrcon register controls the operation of the reference as shown in register 20-1. the block dia- gram is given in figure 20-1. the comparator reference supply voltage can come from either v dd or v ss , or the external v ref + and v ref - that are multiplexed with ra3 and ra2. the comparator reference supply voltage is controlled by the cvrss bit. 20.1 configuring the comparator voltage reference the comparator voltage reference can output 16 dis- tinct voltage levels for each range. the equations used to calculate the output of the comparator voltage ref- erence are as follows: if cvrr = 1: cv ref = (cv r <3:0>/24) x cv rsrc if cvrr = 0: cv ref = (cv dd x 1/4) + (cv r <3:0>/32) x cv rsrc the settling time of the comparator voltage reference must be considered when changing the cv ref output (section 25.0). register 20-1: vrcon register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 vren vroe vrr vrss vr3 vr2 vr1 vr0 bit 7 bit 0 bit 7 vren : comparator voltage reference enable 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 vroe : comparator v ref output enable 1 =cv ref voltage level is also output on the rf5/an10/cv ref pin 0 =cv ref voltage is disconnected from the rf5/an10/cv ref pin bit 5 vrr : comparator v ref range selection 1 = 0.00 cv rsrc to 0.75 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 vrss : comparator v ref source selection 1 = comparator reference source cv rsrc = v ref +-v ref - 0 = comparator reference source cv rsrc = v dd -v ss bit 3-0 vr3:vr0: comparator v ref value selection 0 vr3:vr0 15 when vrr = 1: cv ref = (vr<3:0>/ 24) ? (cv rsrc ) when vrr = 0: cv ref = 1/4 ? (cv rsrc ) + (vr3:vr0/ 32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown pic18cxx8 ds30475a-page 244 advanced information ? 2000 microchip technology inc. figure 20-1: voltage reference block diagram note: r is defined in section 25.0. cv rr 8r cv r 3 cv r 0 (from vrcon<3:0>) 16-1 analog mux 8r r r r r cv ren cv ref 16 stages cvrss=0 v dd v ref + vrss=0 vrss=1 v ref - cvrss=1 ? 2000 microchip technology inc. advanced information ds30475a-page 245 pic18cxx8 20.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 20-1) keep v ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the v ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 25.0. 20.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the vrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 20.4 effects of a reset a device reset disables the voltage reference by clearing bit vren (vrcon register). this reset also disconnects the reference from the ra2 pin by clearing bit vroe (vrcon register) and selects the high volt- age range by clearing bit cv rr (vrcon register). the vrss value select bits, cvrcon<3:0>, are also cleared. 20.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the trisf<5> bit is set and the vroe bit (vrcon regis- ter) is set. enabling the voltage reference output onto the rf5 pin, with an input signal present, will increase current consumption. connecting rf5 as a digital output with vrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage refer- ence output for external connections to v ref . figure 20-2 shows an example buffering technique. figure 20-2: voltage reference output buffer example table 20-1: registers associated with comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the voltage reference configuration vrcon<3:0> and vrcon<5>. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets vrcon vren vroe vrr vrss vr3 vr2 vr1 vr0 0000 0000 0000 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0000 0000 0000 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 1111 1111 1111 1111 pic18cxx8 ds30475a-page 246 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 247 pic18cxx8 21.0 low voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do "housekeeping tasks" before the device voltage exits the valid operating range. this can be done using the low voltage detect module. this module is software programmable circuitry, where a device voltage trip point can be specified (internal ref- erence voltage or external voltage input). when the voltage of the device becomes lower than the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the interrupt vec- tor address and the software can then respond to that interrupt source. the low voltage detect circuitry is completely under software control. this allows the circuitry to be "turned off" by the software, which minimizes the current con- sumption for the device. figure 21-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . t b - t a is the total time for shutdown. figure 21-1: typical low voltage detect application figure 21-2 shows the block diagram for the lvd mod- ule. a comparator uses an internally generated refer- ence voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit (pir registers) is set. each node in the resister divider represents a ? trip point ? voltage. the ? trip point ? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array (or external lvdin input pin) is equal to the voltage generated by the internal voltage reference module. the comparator then gener- ates an interrupt signal setting the lvdif bit. this volt- age is software programmable to any one of 16 values (see figure 21-2). the trip point is selected by pro- gramming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 21-2: low voltage detect (lvd) block diagram time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating range legend: lvdif v dd 16 to 1 mux lvden lvd control register internally generated reference voltage lvdin pic18cxx8 ds30475a-page 248 advanced information ? 2000 microchip technology inc. 21.1 c ontrol register the low voltage detect control register (register 21-1) controls the operation of the low voltage detect circuitry. register 21-1: lvdcon register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as '0' bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low voltage detect logic will not generate the interrupt flag at the spec- ified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.5v min - 4.77v max. 1101 = 4.2v min - 4.45v max. 1100 = 4.0v min - 4.24v max.; reserved on pic18cxx8 1011 = 3.8v min - 4.03v max.; reserved on pic18cxx8 1010 = 3.6v min - 3.82v max.; reserved on pic18cxx8 1001 = 3.5v min - 3.71v max.; reserved on pic18cxx8 1000 = 3.3v min - 3.50v max.; reserved on pic18cxx8 0111 = 3.0v min - 3.18v max.; reserved on pic18cxx8 0110 = 2.8v min - 2.97v max.; reserved on pic18cxx8 0101 = 2.7v min - 2.86v max.; reserved on pic18cxx8 0100 = 2.5v min - 2.65v max.; reserved on pic18cxx8 0011 = reserved on pic18cxx8 and pic18lcxx8 0010 = reserved on pic18cxx8 and pic18lcxx8 0001 = reserved on pic18cxx8 and pic18lcxx8 0000 = reserved on pic18cxx8 and pic18lcxx8 note: lvdl3:lvdl0 modes which result in a trip point below the valid operating voltage of the device are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por ? 1 ? = bit is set ? 0 ? = bit is cleared x = bit is unknown ? 2000 microchip technology inc. advanced information ds30475a-page 249 pic18cxx8 21.2 operatio n depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be con- stantly operating. to decrease current consumption, the lvd circuitry only needs to be enabled for short periods, where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to setup the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register), which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 21-3 shows typical waveforms that the lvd module may be used to detect. figure 21-3: low voltage detect waveforms . v lvd v dd lvdif v lvd v dd enable lvd internally generated 50 ms lvdif may not be set enable lvd 50 ms lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable pic18cxx8 ds30475a-page 250 advanced information ? 2000 microchip technology inc. 21.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires time to become stable before a low voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter #36. the low voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 21-3. 21.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d022b. 21.3 external analog voltage input the lvd module has an additional feature that allows the user to supply the trip point voltage to the module from an external source (the lvdin pin). the lvdin pin is used as the trip point when the lvdl3:lvdl0 bits = ? 1111 ? . this state connects the lvdin pin voltage to the comparator. the other comparator input is con- nected to an internal reference voltage source. 21.4 operation during s leep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address if interrupts have been glo- bally enabled. 21.5 effects of a r eset a device reset forces all registers to their reset state. this forces the lvd module to be turned off. ? 2000 microchip technology inc. advanced information ds30475a-page 251 pic18cxx8 22.0 special features of the cpu there are several features intended to maximize sys- tem reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection: osc selection reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - programmable brown-out reset (bor) interrupts watchdog timer (wdt) sleep code protection id locations in-circuit serial programming pic18cxx8 devices have a watchdog timer, which is permanently enabled via the configuration bits or it can be software-controlled. it runs off its own rc oscillator for added reliability. there are two timers that offer nec- essary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay on power-up only, designed to keep the part in reset while the power supply stabilizes. with these two timers on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to fit the application. the rc oscillator option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options. 22.1 configuration bits the configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h - 3fffffh), which can only be accessed using table reads and table writes. table 22-1: configuration bits and device id ? s filename bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300000h config1l cp cp cp cp cp cp cp cp 1111 1111 300001h config1h r r oscsen ? ? fosc2 fosc1 fosc0 111- -111 300002h config2l ? ? ? ? borv1 borv0 boden pwrten ---- 1111 300003h config2h ? ? ? ? wdtps2 wdtps1 wdtps0 wdten ---- 1111 300006h config4l ? ? ? ? ? ? rstvren ---- --11 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 1111 1111 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. grayed cells are unimplemented, read as ? 0 ? . pic18cxx8 ds30475a-page 252 advanced information ? 2000 microchip technology inc. register 22-1: configuration register 1 low (config1l: byte address 0x300000) register 22-2: configuration register 1 high (config1h: byte address 0x300001) r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp cp cp cp cp cp cp cp bit 7 bit 0 bit 7-0 cp: code protection bits (apply when in code protected microcontroller mode) 1 = program memory code protection off 0 = all of program memory code protected legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state r/p-1 r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 reserved reserved oscsen ? ? fosc2 fosc1 fosc0 bit 7 bit 0 bit 7-6 reserved: maintain this bit set bit 5 oscsen : oscillator system clock switch enable bit 1 = oscillator system clock switch option is disabled (main oscillator is source) 0 = oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 unimplemented: read as ? 0 ? bit 2-0 fosc2:fosc0 : oscillator selection bits 111 = rc oscillator w/ osc2 configured as ra6 110 = hs4 oscillator with pll enabled/clock frequency = (4 x fosc) 101 = ec oscillator w/ osc2 configured as ra6 100 = ec oscillator w/ osc2 configured as divide by 4 clock output 011 = rc oscillator 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state ? 2000 microchip technology inc. advanced information ds30475a-page 253 pic18cxx8 register 22-3: configuration register 2 low (config2l: byte address 0x300002) register 22-4: configuration register 2 high (config2h: byte address 0x300003) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? borv1 borv0 boren pwrten bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-2 borv1:borv0: brown-out reset voltage bits 11 =v bor set to 2.5v 10 =v bor set to 2.7v 01 =v bor set to 4.2v 00 =v bor set to 4.5v bit 1 boren: brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled bit 0 pwrten : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note 1: enabling brown-out reset automatically enables the power-up timer (pwrt), regardless of the value of bit pwrten . ensure the power-up timer is enabled any time brown-out reset is enabled. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-1 wdtps2:wdtps0: watchdog timer postscale select bits 000 = 1:128 001 = 1:64 010 = 1:32 011 = 1:16 100 = 1:8 101 = 1:4 110 = 1:2 111 = 1:1 bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state pic18cxx8 ds30475a-page 254 advanced information ? 2000 microchip technology inc. register 22-5: configuration register 4 low (config4l: byte address 0x300006) u-0 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 ? ? ? ? ? ? reserved stvren bit 7 bit 0 bit 7-2 unimplemented: read as ? 0 ? bit 1 reserved: maintain this bit set bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = value when device is unprogrammed u = unchanged from programmed state ? 2000 microchip technology inc. advanced information ds30475a-page 255 pic18cxx8 22.2 watchdog timer (wdt) the watchdog timer is a free running on-chip rc oscil- lator, which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clki pin. that means that the wdt will run, even if the clock on the osc1/clki and osc2/clko/ra6 pins of the device has been stopped; for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset (watchdog timer reset). if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation (watch- dog timer wake-up). the to bit in the rcon register will be cleared upon a wdt time-out. the watchdog timer is enabled/disabled by a device configuration bit. if the wdt is enabled, software exe- cution may not disable this function. when the wdten configuration bit is cleared, the swdten bit enables/disables the operation of the wdt. the wdt time-out period values may be found in the electrical specifications section under parameter #31. values for the wdt postscaler may be assigned using the configuration bits. 22.2.1 control register register 22-6 shows the wdtcon register. this is a readable and writable register, which contains a control bit that allows software to override the wdt enable configuration bit, only when the configuration bit has disabled the wdt. register 22-6: wdtcon register note: the clrwdt and sleep instructions clear the wdt and the postscaler if assigned to the wdt, and prevent it from timing out and generating a device reset condition. note: when a clrwdt instruction is executed and the prescaler is assigned to the wdt, the prescaler count will be cleared, but the prescaler assignment is not changed. u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? swdten bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is turned off if the wdten configuration bit in the configuration register = ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ? 0 ? - n = value at por pic18cxx8 ds30475a-page 256 advanced information ? 2000 microchip technology inc. 22.2.2 wdt postscaler the wdt has a postscaler that can extend the wdt reset period. the postscaler is selected at the time of the device programming, by the value written to the config2h configuration register. figure 22-1: watchdog timer block diagram table 22-2: summary of watchdog timer registers postscaler wdt timer wdten 8 - to - 1 mux wdtps2:wdtps0 wdt time-out 8 swdten bit note: wdps2:wdps0 are bits in a configuration register. configuration bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h ? ? ? ? wdtps2 wdtps2 wdtps0 wdten rcon ipen lwrt ? ri to pd por bor wdtcon ? ? ? ? ? ? ? swdten legend: shaded cells are not used by the watchdog timer. ? 2000 microchip technology inc. advanced information ds30475a-page 257 pic18cxx8 22.3 power-down mode (sleep) power-down mode is entered by executing a sleep instruction. upon entering into power-down mode, the following actions are performed: 1. watchdog timer is cleared and kept running. 2. pd bit in rcon register is cleared. 3. to bit in rcon register is set. 4. oscillator driver is turned off. 5. i/o ports maintain the status they had before the sleep instruction was executed. to achieve lowest current consumption, follow these steps before switching to power-down mode: 1. place all i/o pins at either v dd or v ss and ensure no external circuitry is drawing current from i/o pin. 2. power-down a/d and external clocks. 3. pull all hi-impedance inputs to high or low externally. 4. place t0cki at v ss or v dd . 5. current consumption by portb on-chip pull-ups should be taken into account and dis- abled if necessary. the mclr pin must be at a logic high level (v ihmc ). 22.3.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from int pin, rb port change or a peripheral interrupt. the following peripheral interrupts can wake the device from sleep: 1. psp read or write. 2. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 3. tmr3 interrupt. timer3 must be operating as an asynchronous counter. 4. ccp capture mode interrupt. 5. special event trigger (timer1 in asynchronous mode using an external clock). 6. mssp (start/stop) bit detect interrupt. 7. mssp transmit or receive in slave mode (spi/i 2 c). 8. usart rx or tx (synchronous slave mode). 9. a/d conversion (when a/d clock source is rc). 10. activity on can bus receive line. other peripherals cannot generate interrupts, since during sleep, no on-chip clocks are present. external mclr reset will cause a device reset. all other events are considered a continuation of program execution and will cause a "wake-up". the to and pd bits in the rcon register can be used to determine the cause of the device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. the to bit is cleared, if a wdt time-out occurred (and caused wake-up). when the sleep instruction is being executed, the next instruction (pc + 2) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. pic18cxx8 ds30475a-page 258 advanced information ? 2000 microchip technology inc. 22.3.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if an interrupt condition (interrupt flag bit and inter- rupt enable bits are set) occurs before the execu- tion of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt postscaler will not be cleared, the to bit will not be set and pd bits will not be cleared. if the interrupt condition occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt postscaler will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruc- tion should be executed before a sleep instruction. figure 22-2: wake-up from sleep through interrupt (1,2) q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout ( 4 ) int pin intif bit gieh bit instruction flow pc instruction fetched instruction executed pc pc+2 pc+4 inst(pc) = sleep inst(pc - 1) inst(pc + 2) sleep processor in sleep interrupt latency ( 3 ) inst(pc + 4) inst(pc + 2) inst(0008h) inst(000ah) inst(0008h) dummy cycle pc + 4 0008h 000ah dummy cycle t ost ( 2 ) pc+4 note 1: xt, hs or lp oscillator mode assumed. 2: gie set is assumed. in this case, after wake- up, the processor jumps to the interrupt routine. if gie is cleared, execution will continue in-line. 3: t ost = 1024t osc (drawing not to scale). this delay will not occur for rc and ec osc modes. 4: clkout is not available in these oscillator modes, but shown here for timing reference. ? 2000 microchip technology inc. advanced information ds30475a-page 259 pic18cxx8 22.4 program verification/code protection if the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 22.5 id locations five memory locations (200000h - 200004h) are desig- nated as id locations, where the user can store check- sum or other code identification numbers. these locations are accessible during normal execution through the tblrd instruction, or during program/ver- ify. the id locations can be read when the device is code protected. 22.6 i n-circuit serial programming pic18cxx8 microcontrollers can be serially pro- grammed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firm- ware to be programmed. 22.7 device id b its device id bits are located in program memory at 3ffffeh and 3fffffh. the device id bits are used by programmers to retrieve part number and revision information about a device. these registers may also be accessed using a tblrd instruction (register 22-8 and register 22-7). register 22-7: devid1 id register for the pic18cxx8 device (0x3ffffe) register 22-8: devid2 id register for the pic18cxx8 device (0x3fffff) note: microchip technology does not recom- mend code protecting windowed devices. r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 bit 7-5 dev2:dev0 : device id bits these bits are used with the dev10:dev3 bits in the device id register 2 to identify the part number bit 4-0 rev4:rev0 : revision id bits these bits are used to indicate the revision of the device legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = unprogrammed value (x = unknown) r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 bit 7-0 dev10:dev3 : device id bits these bits are used with the dev2:dev0 bits in the device id register 1 to identify the part number legend: r = readable bit p = programmable bit u = unimplemented bit, read as ? 0 ? - n = unprogrammed value (x = unknown) pic18cxx8 ds30475a-page 260 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 261 pic18cxx8 23.0 instruction set summary the pic18cxx8 instruction set adds many enhance- ments to the previous picmicro ? instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations. each single word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18cxx8 instruction set summary in table 23-2 lists byte-oriented , bit-oriented , literal and control operations. table 23-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by the value of ? f ? ) 2. the destination of the result (specified by the value of ? d ? ) 3. the accessed memory (specified by the value of ? a ? ) 'f' represents a file register designator and 'd' repre- sents a destination designator. the file register desig- nator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if 'd' is zero, the result is placed in the wreg register. if 'd' is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by the value of ? f ? ) 2. the bit in the file register (specified by the value of ? b ? ) 3. the accessed memory (specified by the value of ? a ? ) 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' rep- resents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by the value of ? k ? ) the desired fsr register to load the literal value into (specified by the value of ? f ? ) no operand required (specified by the value of ??? ) the control instructions may use some of the following operands: a program memory address (specified by the value of ? n ? ) the mode of the call or return instructions (spec- ified by the value of ? s ? ) the mode of the table read and table write instructions (specified by the value of ? m ? ) no operand required (specified by the value of ??? ) all instructions are a single word, except for four double word instructions. these three instructions were made double word instructions so that all the required infor- mation is available in these 32-bits. in the second word, the 4-msb ? s are 1 ? s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two word branch instructions (if true) would take 3 s. figure 23-1 shows the general formats that the instruc- tions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. the instruction set summary, shown in table 23-2, lists the instructions recognized by the microchip assembler (mpasm tm ). section 23.1 provides a description of each instruction. pic18cxx8 ds30475a-page 262 advanced information ? 2000 microchip technology inc. table 23-1: opcode field descriptions field description a ram access bit a = 0: ram location in access ram (bsr register is ignored) a = 1: ram bank is specified by bsr register access access = 0: ram access bit symbol banked banked = 1: ram access bit symbol bbb bit address within an 8-bit file register (0 to 7) bsr bank select register. used to select the current ram bank. d destination select bit; d = 0: store result in wreg, d = 1: store result in file register f. dest destination either the wreg register or the specified register file location f 8-bit register file address (0x00 to 0xff) f s 12-bit register file address (0x000 to 0xfff). this is the source address. f d 12-bit register file address (0x000 to 0xfff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) label label name mm the mode of the tblptr register for the table read and table write instructions only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tblptr with table reads and writes) n the relative address (2 ? s complement number) for relative branch instructions, or the direct address for call/branch and return instructions prodh product of multiply high byte (register at address 0xff4) prodl product of multiply low byte (register at address 0xff3) s fast call / return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (fast mode) u unused or unchanged (register at address 0xfe8) w w = 0: destination select bit symbol wreg working register (accumulator) (register at address 0xfe8) x don't care (0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location) (register at address 0xff6) tablat 8-bit table latch (register at address 0xff5) tos top-of-stack pc program counter pcl program counter low byte (register at address 0xff9) pch program counter high byte pclath program counter high byte latch (register at address 0xffa) pclatu program counter upper byte latch (register at address 0xffb) gie global interrupt enable bit wdt watchdog timer to time-out bit pd power-down bit c, dc, z, ov, n alu status bits carry, digit carry, zero, overflow, negative [ ] optional ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier) ? 2000 microchip technology inc. advanced information ds30475a-page 263 pic18cxx8 figure 23-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s 1111 15 6 4 0 opcode 15 11 7 0 k (literal) lfsr fsr0, 0x100 f k (literal) 1111 0000 pic18cxx8 ds30475a-page 264 advanced information ? 2000 microchip technology inc. table 23-2: pic18cxx8 instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,a] f [,d] [,a] f [,a] f [,a] f [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f s , f d f [,a] f [,a] f [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,d] [,a] f [,a] f [,d] [,a] add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination)2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2, 6 1, 2, 6 1,2, 6 2, 6 1, 2, 6 4, 6 4, 6 1, 2, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 6 1, 2, 3, 4, 6 4, 6 1, 2, 6 1, 2, 6 1, 6 6 6 1, 2, 6 6 1, 2, 6 6 6 6 1, 2, 6 6 1, 2, 6 4, 6 1, 2, 6 6 bit-oriented file register operations bcf bsf btfsc btfss btg f, b [,a] f, b [,a] f, b [,a] f, b [,a] f [,d] [,a] bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2, 6 1, 2, 6 3, 4, 6 3, 4, 6 1, 2, 6 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip assembler masm automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? according to address of register being used. ? 2000 microchip technology inc. advanced information ds30475a-page 265 pic18cxx8 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine1st word 2nd word clear watchdog timer decimal adjust wreg go to address1st word 2nd word no operation no operation (note 4) pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd table 23-2: pic18cxx8 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip assembler masm automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? according to address of register being used. pic18cxx8 ds30475a-page 266 advanced information ? 2000 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg load fsr(f) with a 12-bit literal (k) move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 23-2: pic18cxx8 instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ? . 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2 word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated. 6: microchip assembler masm automatically defaults destination bit ? d ? to ? 1 ? , while access bit ? a ? defaults to ? 1 ? or ? 0 ? according to address of register being used. ? 2000 microchip technology inc. advanced information ds30475a-page 267 pic18cxx8 23.1 instruction set addlw add literal to w syntax: [ label ] addlw k operands: 0 k 255 operation: (wreg) + k wreg status affected: n,ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of wreg are added to the 8-bit literal ? k ? and the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to w example : addlw 0x15 before instruction wreg = 0x10 n=? ov = ? c=? dc = ? z=? after instruction wreg = 0x25 n=0 ov = 0 c=0 dc = 0 z=0 addwf add w to f syntax: [ label ] addwf f [,d] [,a] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) + (f) dest status affected: n,ov, c, dc, z encoding: 0010 01da ffff ffff description: add wreg to register ? f ? . if ? d ? is 0, the result is stored in wreg. if ? d ? is 1, the result is stored back in reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : addwf reg, w before instruction wreg = 0x17 reg = 0xc2 n=? ov = ? c=? dc = ? z=? after instruction wreg = 0xd9 reg = 0xc2 n=1 ov = 0 c=0 dc = 0 z=0 pic18cxx8 ds30475a-page 268 advanced information ? 2000 microchip technology inc. addwfc add wreg and carry bit to f syntax: [ label ] addwfc f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) + (f) + (c) dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add wreg, the carry flag and data memory location ? f ? . if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed in data memory location 'f'. if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : addwfc reg, w before instruction c=1 reg = 0x02 wreg = 0x4d n= ? ov = ? dc = ? z=? after instruction c=0 reg = 0x02 wreg = 0x50 n= 0 ov = 0 dc = 0 z=0 andlw and literal with wreg syntax: [ label ] andlw k operands: 0 k 255 operation: (wreg) .and. k wreg status affected: n,z encoding: 0000 1011 kkkk kkkk description: the contents of wreg are and ? ed with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to w example : andlw 0x5f before instruction wreg = 0xa3 n= ? z=? after instruction wreg = 0x03 n= 0 z=0 ? 2000 microchip technology inc. advanced information ds30475a-page 269 pic18cxx8 andwf and wreg with f syntax: [ label ] andwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .and. (f) dest status affected: n,z encoding: 0001 01da ffff ffff description: the contents of wreg are and ? ed with register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : andwf reg, w before instruction wreg = 0x17 reg = 0xc2 n= ? z=? after instruction wreg = 0x02 reg = 0xc2 n= 0 z=0 bc branch if carry syntax: [ label ] bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here+12) if carry = 0; pc = address (here+2) pic18cxx8 ds30475a-page 270 advanced information ? 2000 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit 'b' in register 'f' is cleared. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? = 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here+2) ? 2000 microchip technology inc. advanced information ds30475a-page 271 pic18cxx8 bnc branch if not carry syntax: [ label ] bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here+2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here+2) pic18cxx8 ds30475a-page 272 advanced information ? 2000 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here+2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here+2) ? 2000 microchip technology inc. advanced information ds30475a-page 273 pic18cxx8 bra unconditional branch syntax: [ label ] bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2 ? s complement number ? 2n ? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two- cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit 'b' in register 'f' is set. if ? a ? is 0 access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : bsf flag_reg, 7, 1 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a pic18cxx8 ds30475a-page 274 advanced information ? 2000 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f, b [,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit 'b' in register ? f' is 0, then the next instruction is skipped. if bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc : : flag, 1, access before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f, b [,a] operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit 'b' in register 'f' is 1 then the next instruction is skipped. if bit 'b' is 1, then the next instruction fetched during the current instruc- tion execution, is discarded and an nop is executed instead, making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfss : : flag, 1, access before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) ? 2000 microchip technology inc. advanced information ds30475a-page 275 pic18cxx8 btg bit toggle f syntax: [ label ] btg f, b [,a] operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ? b ? in data memory location ? f ? is inverted. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : btg portc, 4 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65] bov branch if overflow syntax: [ label ] bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ? , then the program will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here+2) pic18cxx8 ds30475a-page 276 advanced information ? 2000 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ? , then the pro- gram will branch. the 2 ? s complement number ? 2n ? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ? n ? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ? n ? process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here+2) call subroutine call syntax: [ label ] call k [,s] operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (wreg) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2m byte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ? s ? = 1, the wreg, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if 's' = 0, no update occurs (default). then the 20-bit value ? k ? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? <7:0>, push pc to stack read literal ? k ? <19:8>, write to pc no operation no operation no operation no operation example : here call there, fast before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = wreg bsrs = bsr statuss = status ? 2000 microchip technology inc. advanced information ds30475a-page 277 pic18cxx8 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : clrf flag_reg before instruction flag_reg = 0x5a z=? after instruction flag_reg = 0x00 z=0 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? wdt postscaler = ? to =? pd =? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1 pic18cxx8 ds30475a-page 278 advanced information ? 2000 microchip technology inc. comf complement f syntax: [ label ] comf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n,z encoding: 0001 11da ffff ffff description: the contents of register ? f ? are com- plemented. if ? d ? is 0 the result is stored in w. if ? d ? is 1 the result is stored back in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : comf reg before instruction reg = 0x13 n=? z=? after instruction reg = 0x13 wreg = 0xec n=1 z=0 (f) cpfseq compare f with wreg, skip if f = wreg syntax: [ label ] cpfseq f [,a] operands: 0 f 255 a [0,1] operation: (f) ? (wreg), skip if (f) = (wreg) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location 'f' to the contents of w by performing an unsigned subtraction. if 'f' = wreg , then the fetched instruction is discarded and an nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg nequal : equal : before instruction pc address = here wreg = ? reg = ? after instruction if reg = wreg; pc = address (equal) if reg wreg; pc = address (nequal) ? 2000 microchip technology inc. advanced information ds30475a-page 279 pic18cxx8 cpfsgt compare f with wreg, skip if f > wreg syntax: [ label ] cpfsgt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( wreg), skip if (f) > (wreg) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ? f ? to the contents of the wreg by performing an unsigned subtraction. if the contents of ? f ? are greater than the contents of , then the fetched instruction is discarded and a nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) wreg = ? after instruction if reg > wreg; pc = address (greater) if reg wreg; pc = address (ngreater) cpfslt compare f with wreg, skip if f < wreg syntax: [ label ] cpfslt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( wreg), skip if (f) < (wreg) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location 'f' to the contents of w by performing an unsigned subtraction. if the contents of 'f' are less than the contents of wreg, then the fetched instruction is discarded and a nop is executed instead making this a two-cycle instruction. if ? a ? is 0, the access bank will be selected. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg nless : less : before instruction pc = address (here) wreg = ? after instruction if reg < wreg; pc = address (less) if reg wreg; pc = address (nless) pic18cxx8 ds30475a-page 280 advanced information ? 2000 microchip technology inc. daw decimal adjust wreg register syntax: [ label ] daw operands: none operation: if [wreg<3:0> >9] or [dc = 1] then (wreg<3:0>) + 6 w<3:0>; else ( wreg<3:0>) w<3:0>; if [wreg<7:4> >9] or [c = 1] then ( wreg<7:4>) + 6 wreg<7:4>; else (wreg<7:4>) wreg<7:4>; status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight bit value in wreg resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register wreg process data write wreg example1 : daw before instruction wreg = 0xa5 c=0 dc = 0 after instruction wreg = 0x05 c=1 dc = 0 example 2 : before instruction wreg = 0xce c=0 dc = 0 after instruction wreg = 0x34 c=1 dc = 0 decf decrement f syntax: [ label ] decf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c,dc,n,ov,z encoding: 0000 01da ffff ffff description: decrement register 'f'. if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : decf cnt before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 ? 2000 microchip technology inc. advanced information ds30475a-page 281 pic18cxx8 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register 'f' are dec- remented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is 0, the next instruc- tion, which is already fetched, is discarded, and a nop is executed instead making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here+2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register 'f' are dec- remented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruction, which is already fetched, is discarded, and a nop is executed instead making it a two- cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp zero : nzero : before instruction temp = ? after instruction temp = temp - 1, if temp = 0; pc = address (zero ) if temp 0; pc = address (nzero) pic18cxx8 ds30475a-page 282 advanced information ? 2000 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2m byte memory range. the 20-bit value ? k ? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? <7:0>, no operation read literal ? k ? <19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c,dc,n,ov,z encoding: 0010 10da ffff ffff description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : incf cnt before instruction cnt = 0xff z=0 c=? dc = ? after instruction cnt = 0x00 z=1 c=1 dc = 1 ? 2000 microchip technology inc. advanced information ds30475a-page 283 pic18cxx8 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ? f ? are incremented. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed back in register ? f ? (default). if the result is 0, the next instruc- tion, which is already fetched, is discarded, and a nop is executed instead making it a two-cycle instruction. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [, d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register 'f' are incremented. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if the result is not 0, the next instruction, which is already fetched, is discarded, and a nop is executed instead making it a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero) pic18cxx8 ds30475a-page 284 advanced information ? 2000 microchip technology inc. iorlw inclusive or literal with wreg syntax: [ label ] iorlw k operands: 0 k 255 operation: (wreg) .or. k wreg status affected: n,z encoding: 0000 1001 kkkk kkkk description: the contents of wreg are or ? ed with the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to w example : iorlw 0x35 before instruction wreg = 0x9a n=? z=? after instruction wreg = 0xbf n=1 z=0 iorwf inclusive or wreg with f syntax: [ label ] iorwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .or. (f) dest status affected: n,z encoding: 0001 00da ffff ffff description: inclusive or w with register 'f'. if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : iorwf result, w before instruction result = 0x13 wreg = 0x91 n=? z=? after instruction result = 0x13 wreg = 0x93 n=1 z=0 ? 2000 microchip technology inc. advanced information ds30475a-page 285 pic18cxx8 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ? k ? is loaded into the file select register pointed to by ? f ? words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? msb process data write literal ? k ? msb to fsrfh decode read literal ? k ? lsb process data write literal ? k ? to fsrfl example : lfsr fsr2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n,z encoding: 0101 00da ffff ffff description: the contents of register ? f ? is moved to a destination dependent upon the status of ? d ? . if 'd' is 0, the result is placed in wreg. if 'd' is 1, the result is placed back in register 'f' (default). location 'f' can be any- where in the 256 byte bank. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write w example : movf reg, w before instruction reg = 0x22 wreg = 0xff n=? z=? after instruction reg = 0x22 wreg = 0x22 n=0 z=0 pic18cxx8 ds30475a-page 286 advanced information ? 2000 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register ? f s ? are moved to destination register ? f d ? . location of source ? f s ? can be anywhere in the 4096 byte data space (000h to fffh), and location of destination ? f d ? can also be any- where from 000h to fffh. either source or destination can be wreg (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ? f ? (src) process data no operation decode no operation no dummy read no operation write register ? f ? (dest) example : movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal ? k ? is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write literal ? k ? to bsr example : movlb 0x05 before instruction bsr register = 0x02 after instruction bsr register = 0x05 ? 2000 microchip technology inc. advanced information ds30475a-page 287 pic18cxx8 movlw move literal to wreg syntax: [ label ] movlw k operands: 0 k 255 operation: k wreg status affected: none encoding: 0000 1110 kkkk kkkk description: the eight bit literal ? k ? is loaded into wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to w example : movlw 0x5a after instruction wreg = 0x5a movwf move wreg to f syntax: [ label ] movwf f [,a] operands: 0 f 255 a [0,1] operation: (wreg) f status affected: none encoding: 0110 111a ffff ffff description: move data from wreg to register ? f ? . location ? f ? can be anywhere in the 256 byte bank. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : movwf reg before instruction wreg = 0x4f reg = 0xff after instruction wreg = 0x4f reg = 0x4f pic18cxx8 ds30475a-page 288 advanced information ? 2000 microchip technology inc. mullw multiply literal with wreg syntax: [ label ] mullw k operands: 0 k 255 operation: (wreg) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is car- ried out between the contents of wreg and the 8-bit literal ? k ? . the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. wreg is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write registers prodh: prodl example : mullw 0xc4 before instruction wreg = 0xe2 prodh = ? prodl = ? after instruction wreg = 0xe2 prodh = 0xad prodl = 0x08 mulwf multiply wreg with f syntax: [ label ] mulwf f [,a] operands: 0 f 255 a [0,1] operation: (wreg) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is car- ried out between the contents of wreg and the register file loca- tion ? f ? . the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both wreg and ? f ? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write registers prodh: prodl example : mulwf reg before instruction wreg = 0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction wreg = 0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94 ? 2000 microchip technology inc. advanced information ds30475a-page 289 pic18cxx8 negf negate f syntax: [ label ] negf f [,a] operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n,ov, c, dc, z encoding: 0110 110a ffff ffff description: location ? f ? is negated using two ? s complement. the result is placed in the data memory location 'f'. if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write register ? f ? example : negf reg before instruction reg = 0011 1010 [0x3a] n=? ov = ? c=? dc = ? z=? after instruction reg = 1100 0110 [0xc6] n=1 ov = 0 c=0 dc = 0 z=0 nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none. pic18cxx8 ds30475a-page 290 advanced information ? 2000 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previ- ous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc+2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc+2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implement- ing a software stack by modifying tos, and then push it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc+2 onto return stack no operation no operation example : push before instruction tos = 00345ah pc = 000124h after instruction pc = 000126h tos = 000126h stack (1 level down) = 00345ah ? 2000 microchip technology inc. advanced information ds30475a-page 291 pic18cxx8 rcall relative call syntax: [ label ] rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc+2) is pushed onto the stack. then, add the 2 ? s complement number ? 2n ? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? n ? push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here+2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value pic18cxx8 ds30475a-page 292 advanced information ? 2000 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged. status affected: none encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting the either the high or low priority global interrupt enable bit. if ? s ? = 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ? s ? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos wreg = ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to wreg syntax: [ label ] retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data pop pc from stack, write to w no operation no operation no operation no operation example : call table ; wreg contains table ; offset value ; wreg now has ; table value : table addwf pcl ; wreg = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction wreg = 0x07 after instruction wreg = value of kn ? 2000 microchip technology inc. advanced information ds30475a-page 293 pic18cxx8 return return from subroutine syntax: [ label ] return [s] operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ? s ? = 1, the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, wreg, status and bsr. if ? s ? = 0, no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after call pc = tos return fast before instruction wrg = 0x04 status = 0x00 bsr = 0x00 after instruction wreg = 0x04 status = 0x00 bsr = 0x00 pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f pic18cxx8 ds30475a-page 294 advanced information ? 2000 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f ? 2000 microchip technology inc. advanced information ds30475a-page 295 pic18cxx8 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f pic18cxx8 ds30475a-page 296 advanced information ? 2000 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from wreg with borrow syntax: [ label ] subfwb f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) ? (f) ? (c ) dest status affected: n,ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register 'f' and carry flag (borrow) from wreg (2 ? s comple- ment method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored in register 'f' (default) . if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination ? 2000 microchip technology inc. advanced information ds30475a-page 297 pic18cxx8 subfwb (cont.) example 1 : subfwb reg before instruction reg = 3 wreg = 2 c=1 after instruction reg = 0xff wreg = 2 c=0 z=0 n = 1 ; result is negative example 2 : subfwb reg before instruction reg = 2 wreg = 5 c=1 after instruction reg = 2 wreg = 3 c=1 z=0 n = 0 ; result is positive example 3 : subfwb reg before instruction reg = 1 wreg = 2 c=0 after instruction reg = 0 wreg = 2 c=1 z = 1 ; result is zero n=0 sublw subtract wreg from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k ? (wreg) wreg status affected: n,ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: wreg is subtracted from the eight bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to w example 1: sublw 0x02 before instruction wreg = 1 c=? after instruction wreg = 1 c = 1 ; result is positive z=0 n=0 example 2 : sublw 0x02 before instruction wreg = 2 c=? after instruction wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : sublw 0x02 before instruction wreg = 3 c=? after instruction wreg = 0xff ; (2 ? s complement) c = 0 ; result is negative z=0 n=1 pic18cxx8 ds30475a-page 298 advanced information ? 2000 microchip technology inc. subwf subtract wreg from f syntax: [ label ] subwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (wreg) dest status affected: n,ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract wreg from register 'f' (2 ? s complement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in register 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination subwf subtract wreg from f (cont ? d) example 1 : subwf reg before instruction reg = 3 wreg = 2 c=? after instruction reg = 1 wreg = 2 c = 1 ; result is positive z=0 n=0 example 2 : subwf reg, w before instruction reg = 2 wreg = 2 c=? after instruction reg = 2 wreg = 0 c = 1 ; result is zero z=1 n=0 example 3 : subwf reg before instruction reg = 1 wreg = 2 c=? after instruction reg = 0xff ;(2 ? s complement) wreg = 2 c = 0 ; result is negative z=0 n=1 ? 2000 microchip technology inc. advanced information ds30475a-page 299 pic18cxx8 subwfb subtract wreg from f with borrow syntax: [ label ] subwfb f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (wreg) ? (c ) dest status affected: n,ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract wreg and the carry flag (borrow) from register 'f' (2 ? s com- plement method). if 'd' is 0, the result is stored in wreg. if 'd' is 1, the result is stored back in reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination subwfb subtract wreg from f with borrow (cont ? d) example 1 : subwfb reg before instruction reg = 0x19 ( 0001 1001 ) wreg = 0x0d ( 0000 1101 ) c=1 after instruction reg = 0x0c ( 0000 1011 ) wreg = 0x0d ( 0000 1101 ) c=1 z=0 n = 0 ; result is positive example 2 : subwfb reg, w before instruction reg = 0x1b ( 0001 1011 ) wreg = 0x1a ( 0001 1010 ) c=0 after instruction reg = 0x1b ( 0001 1011 ) wreg = 0x00 c=1 z = 1 ; result is zero n=0 example 3 : subwfb reg before instruction reg = 0x03 ( 0000 0011 ) wreg = 0x0e ( 0000 1101 ) c=1 after instruction reg = 0xf5 ( 1111 0100 ) [2 ? s comp] wreg = 0x0e ( 0000 1101 ) c=0 z=0 n = 1 ; result is negative pic18cxx8 ds30475a-page 300 advanced information ? 2000 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of reg- ister ? f ? are exchanged. if ? d ? is 0, the result is placed in wreg. if ? d ? is 1, the result is placed in register ? f ? (default). if ? a ? is 0, the access bank will be selected, overriding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : swapf reg before instruction reg = 0x53 after instruction reg = 0x35 ? 2000 microchip technology inc. advanced information ds30475a-page 301 pic18cxx8 tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr - no change; if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) +1 tblptr; if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) -1 tblptr; if tblrd +*, (tblptr) +1 tblptr; (prog mem (tblptr)) tablat; status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. tblptr[0] = 0: least significant byte of program memory word tblptr[0] = 1: most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (cont ? d) example 1 : tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 example 2 : tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358 pic18cxx8 ds30475a-page 302 advanced information ? 2000 microchip technology inc. tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) prog mem (tblptr) or holding register; tblptr - no change; if tblwt*+, (tablat) prog mem (tblptr) or holding register; (tblptr) +1 tblptr; if tblwt*-, (tablat) prog mem (tblptr) or holding register; (tblptr) -1 tblptr; if tblwt+*, (tblptr) +1 tblptr; (tablat) prog mem (tblptr) or holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to program the contents of program memory (p.m.). the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbtye address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0:least significant byte of program memory word tblptr[0] = 1:most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 (many if long write is to on-chip eprom program memory) q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register or memory) tblwt table write (continued) example 1 : tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 memory(0x00a356) = 0x55 example 2 : tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a memory(0x01389a) = 0xff memory(0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b memory(0x01389a) = 0xff memory(0x01389b) = 0x34 ? 2000 microchip technology inc. advanced information ds30475a-page 303 pic18cxx8 tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ? f ? = 0, the next instruction, fetched during the current instruc- tion execution, is discarded and a nop is executed making this a two- cycle instruction. if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt nzero : zero : before instruction pc = address ( here ) after instruction if cnt = 0x00, pc = address (zero) if cnt 0x00, pc = address (nzero) xorlw exclusive or literal with wreg syntax: [ label ] xorlw k operands: 0 k 255 operation: (wreg) .xor. k wreg status affected: n,z encoding: 0000 1010 kkkk kkkk description: the contents of wreg are xor ? ed with the 8-bit literal 'k'. the result is placed in wreg. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ? k ? process data write to wreg example : xorlw 0xaf before instruction wreg = 0xb5 n=? z=? after instruction wreg = 0x1a n=0 z=0 pic18cxx8 ds30475a-page 304 advanced information ? 2000 microchip technology inc. xorwf exclusive or wreg with f syntax: [ label ] xorwf f [ ,d [,a] ] operands: 0 f 255 d [0,1] a [0,1] operation: (wreg) .xor. (f) dest status affected: n,z encoding: 0001 10da ffff ffff description: exclusive or the contents of wreg with register ? f ? . if ? d ? is 0, the result is stored in wreg. if ? d ? is 1, the result is stored back in the reg- ister 'f' (default). if ? a ? is 0, the access bank will be selected, over- riding the bsr value. if ? a ? is 1, the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ? f ? process data write to destination example : xorwf reg before instruction reg = 0xaf wreg = 0xb5 n=? z=? after instruction reg = 0x1a wreg = 0xb5 n=0 z=0 ? 2000 microchip technology inc. advanced information ds30475a-page 305 pic18cxx8 24.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm linker/mplib tm librarian simulators - mplab sim software simulator emulators - mplab ice 2000 in-circuit emulator - icepic ? in-circuit emulator in-circuit debugger - mplab icd for pic16f877 device programmers -pro mate ? ii universal device programmer - picstart ? plus entry-level development programmer low cost demonstration boards - picdem tm 1 demonstration board - picdem 2 demonstration board - picdem 3 demonstration board - picdem 17 demonstration board -k ee l oq ? demonstration board 24.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. the mplab ide is a windows ? -based application which contains: multiple functionality -editor - simulator - programmer (sold separately) - emulator (sold separately) a full featured editor a project manager customizable tool bar and key mapping a status bar on-line help the mplab ide allows you to: edit your source files (either assembly or ? c ? ) one touch assemble (or compile) and download to picmicro tools (automatically updates all project information) debug using: - source files - absolute listing file - object code the ability to use mplab ide with microchip ? s mplab sim simulator, allows a consistent platform and the ability to easily switch from the cost effective simulator to the full featured emulator with minimal retraining. 24.2 mpasm assembler the mpasm assembler is a full featured universal macro assembler for all picmicro mcu ? s. it can pro- duce absolute code directly in the form of hex files for device programmers, or it can generate relocatable objects for the mplink object linker. the mpasm assembler has a command line interface and a windows shell and can be used as a stand-alone application on a windows 3.x, or greater, system. the mpasm assembler generates relocatable object files, intel ? standard hex files, map files to detail memory usage and symbol reference, an absolute lst file, which contains source lines and generated machine code, and a cod file for debugging. the mpasm assembler features include: mpasm assembler and mplink object linker are integrated into mplab ide projects. mpasm assembler allows user defined macros to be created for streamlined assembly. mpasm assembler allows conditional assembly for multi-purpose source files. mpasm assembler directives allow complete control over the assembly process. 24.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi ? c ? compilers and inte- grated development environments for microchip ? s pic17cxxx and pic18cxxx family of microcontrol- lers, respectively. these compilers provide powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compilers pro- vide symbol information that is compatible with the mplab ide memory display. pic18cxx8 ds30475a-page 306 advanced information ? 2000 microchip technology inc. 24.4 mplink linker/mplib librarian the mplink object linker is a relocatable linker for the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from assembly or c source files, along with pre-compiled libraries, using directives from a linker script. the mplib object librarian is a librarian for pre- compiled code to be used with the mplink object linker. when a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the mplib object librarian manages the creation and modification of library files. the mplink object linker features include: mplink object linker works with mpasm assem- bler and mplab c17 and mplab c18 c compilers. mplink object linker allows all memory areas to be defined as sections to provide link-time flexibility. the mplib object librarian features include: mplib object librarian makes linking easier because single libraries can be included instead of many smaller files. mplib object librarian helps keep code maintain- able by grouping related modules together. mplib object librarian commands allow libraries to be created and modules to be added, listed, replaced, deleted or extracted. 24.5 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc host environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. the execution can be performed in single step, execute until break, or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and the mplab c18 c compilers and the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool. 24.6 mplab ice high performance universal in-circuit emulator with mplab ide the mplab ice universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers (mcus). software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment (ide), which allows editing, ? make ? and download and source debugging from a single environment. interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. the pc platform and microsoft ? windows 3.x/95/98 environment were cho- sen to best make these features available to you, the end user. the mplab ice in-circuit emulator is available in two versions: mplab ice 1000 and mplab ice 2000. the mplab ice 1000 is a basic, low cost emulator system with simple trace capabilities. the mplab ice 2000 is a full featured emulator system with enhanced trace, trigger and data monitoring features. both sys- tems use the same processor modules and will operate across the full operating speed range of the picmicro mcu. 24.7 icepic in-circuit emulator the icepic low cost, in-circuit emulator is a solution for the microchip technology pic16c5x, pic16c6x, pic16c7x and pic16cxxx families of 8-bit one- time-programmable (otp) microcontrollers. the mod- ular system can support different subsets of pic16c5x or pic16cxxx products through the use of inter- changeable personality modules, or daughter boards. the emulator is capable of emulating without target application circuitry being present. ? 2000 microchip technology inc. advanced information ds30475a-page 307 pic18cxx8 24.8 mplab icd in-circuit debugger microchip ? s in-circuit debugger, mplab icd, is a pow- erful, low cost, run-time development tool. this tool is based on the flash pic16f877 and can be used to develop this and other picmicro microcontrollers from the pic16cxxx family. the mplab icd utilizes the in- circuit debugging capability built into the pic16f87x. this feature, along with microchip ? s in-circuit serial programming tm protocol, offers cost effective in-circuit flash programming and debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by watching variables, single-step- ping and setting break points. running at full speed enables testing hardware in real-time. the mplab icd is also a programmer for the flash pic16f87x family. 24.9 pro mate ii universal device programmer the pro mate ii universal device programmer is a full featured programmer, capable of operating in stand- alone mode, as well as pc-hosted mode. the pro mate ii device programmer is ce compliant. the pro mate ii device programmer has program- mable v dd and v pp supplies, which allow it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for instruc- tions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify, or pro- gram picmicro devices. it can also set code-protect bits in this mode. 24.10 picstart plus entry level development programmer the picstart plus development programmer is an easy-to-use, low cost, prototype programmer. it con- nects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer sup- ports all picmicro devices with up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 24.11 picdem 1 low cost picmicro demonstration board the picdem 1 demonstration board is a simple board which demonstrates the capabilities of several of microchip ? s microcontrollers. the microcontrollers sup- ported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the user can program the sample microcon- trollers provided with the picdem 1 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer, and easily test firmware. the user can also connect the picdem 1 demonstration board to the mplab ice in- circuit emulator and download the firmware to the emu- lator for testing. a prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simu- lated analog input, push button switches and eight leds connected to portb. 24.12 picdem 2 low cost pic16cxx demonstration board the picdem 2 demonstration board is a simple dem- onstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcontrollers. all the necessary hardware and soft- ware is included to run the basic demonstration pro- grams. the user can program the sample microcontrollers provided with the picdem 2 demon- stration board on a pro mate ii device programmer, or a picstart plus development programmer and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 2 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c tm bus and separate headers for connection to an lcd module and a keypad. pic18cxx8 ds30475a-page 308 advanced information ? 2000 microchip technology inc. 24.13 picdem 3 low cost pic16cxxx demonstration board the picdem 3 demonstration board is a simple dem- onstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with an lcd mod- ule. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers pro- vided with the picdem 3 demonstration board on a pro mate ii device programmer, or a picstart plus development programmer with an adapter socket, and easily test firmware. the mplab ice in-circuit emula- tor may also be used with the picdem 3 demonstration board to test firmware. a prototype area has been pro- vided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem 3 demonstration board is an lcd panel, with 4 commons and 12 segments, that is capable of dis- playing time, temperature and day of the week. the picdem 3 demonstration board provides an additional rs-232 interface and windows 3.1 software for show- ing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. 24.14 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756, pic17c762 and pic17c766. all neces- sary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. a programmed sample is included and the user may erase it and program it with the other sample programs using the pro mate ii device programmer, or the picstart plus development programmer, and easily debug and test the sample code. in addition, the picdem 17 dem- onstration board supports down-loading of programs to and executing out of external flash memory on board. the picdem 17 demonstration board is also usable with the mplab ice in-circuit emulator, or the picmaster emulator and all of the sample programs can be run and modified using either emulator. addition- ally, a generous prototype area is available for user hardware. 24.15 k ee l oq evaluation and programming tools k ee l oq evaluation and programming tools support microchip ? s hcs secure data products. the hcs evaluation kit includes an lcd display to show chang- ing codes, a decoder to decode transmissions and a programming interface to program test transmitters. ? 2000 microchip technology inc. advanced information ds30475a-page 309 pic18cxx8 table 24-1: development tools from microchip pic12cxxx pic14000 pic16c5x pic16c6x pic16cxxx pic16f62x pic16c7x pic16c7xx pic16c8x pic16f8xx pic16c9xx pic17c4x pic17c7xx pic18cxx2 24cxx/ 25cxx/ 93cxx hcsxxx mcrfxxx mcp2510 software tools mplab ? integrated development environment mplab ? c17 c compiler mplab ? c18 c compiler mpasm tm assembler/ mplink tm object linker emulators mplab ? ice in-circuit emulator ** icepic tm in-circuit emulator debugger mplab ? icd in-circuit debugger * * programmers picstart ? plus entry level development programmer ** pro mate ? ii universal device programmer ** demo boards and eval kits picdem tm 1 demonstration board ? picdem tm 2 demonstration board ? ? picdem tm 3 demonstration board picdem tm 14a demonstration board picdem tm 17 demonstration board k ee l oq ? evaluation kit k ee l oq ? transponder kit microid tm programmer ? s kit 125 khz microid tm developer ? s kit 125 khz anticollision microid tm developer ? s kit 13.56 mhz anticollision microid tm developer ? s kit mcp2510 can developer ? s kit * contact the microchip technology inc. web site at www.microchip.com for information on how to use the mplab ? icd in-circuit debugger (dv164001) with pic16c62, 63, 64, 65, 72, 73, 74, 76, 77. ** contact microchip technology inc. for availability date. pic18cxx8 ds30475a-page 310 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 311 pic18cxx8 25.0 electrical characteristics absolute maximum ratings ( ? ) ambient temperature under bias................................................................................................. ............-55 c to +125 c storage temperature ............................................................................................................ .................. -65 c to +150 c voltage on any pin with respect to v ss (except v dd , mclr , and ra4) ......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports (combined) ....................................................................................................200 ma maximum current sourced by all ports (combined) ................................................................................ ...............200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ? low ? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pic18cxx8 ds30475a-page 312 advanced information ? 2000 microchip technology inc. figure 25-1: pic18cxx8 voltage-frequency graph (industrial) figure 25-2: pic18lcxx8 voltage-frequency graph (industrial) frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 40 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic18cxx8 4.2v frequency voltage 6.0 v 5.5 v 4.5 v 4.0 v 2.0 v 40 mhz 5.0 v 3.5 v 3.0 v 2.5 v pic18lcxx8 f max = (20.0 mhz/v) (v ddappmin - 2.5 v) + 6 mhz note: v ddappmin is the minimum voltage of the picmicro ? device in the application. 6 mhz 4.2v ? 2000 microchip technology inc. advanced information ds30475a-page 313 pic18cxx8 25.1 dc characteristi cs pic18lcxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial pic18cxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min typ max units conditions d001 v dd supply voltage pic18lcxx8 2.5 ? 5.5 v hs, xt, rc and lp osc mode d001 pic18cxx8 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ?? v d003 v por v dd start voltage to ensure inter- nal power-on reset signal ?? 0.7 v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ?? v/ms see section on power-on reset for details d005 v bor brown-out reset voltage pic18lcxx8 borv1:borv0 = 11 2.5 ? 2.66 v borv1:borv0 = 10 2.7 ? 2.86 v borv1:borv0 = 01 4.2 ? 4.46 v borv1:borv0 = 00 4.5 ? 4.78 v d005 pic18cxx8 borv1:borv0 = 1x n.a. ? n.a. v not in operating voltage range of device borv1:borv0 = 01 4.2 ? 4.46 v borv1:borv0 = 00 4.5 ? 4.78 v legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode or during a device reset without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss , and all fea- tures that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. pic18cxx8 ds30475a-page 314 advanced information ? 2000 microchip technology inc. 25.1 dc characteristics ( cont ? d) pic18lcxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature-40 c t a +85 c for industrial pic18cxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min typ max units conditions d010 i dd supply current (2,4) pic18lcxx8 ?? 4ma xt, rc, rcio osc configurations f osc = 4 mhz, v dd = 2.5v d010 pic18cxx8 ? ? tbd ma xt, rc, rcio osc configurations f osc = 4 mhz, v dd = 4.2v d010a pic18lcxx8 ?? 48 a lp osc configuration f osc = 32 khz, v dd = 2.5v d010a pic18cxx8 ? ? tbd a lp osc configuration f osc = 32 khz, v dd = 4.2v d010c pic18lcxx8 ?? 45 ma ec, ecio osc configurations, fosc = 40 mhz, v dd = 5.5v d010c pic18cxx8 ? ? 45 ma ec, ecio osc configurations, fosc = 40 mhz, v dd = 5.5v d013 pic18lcxx8 ? ? ? ? ? ? tbd 50 50 ma ma ma hs osc configurations fosc = 6 mhz, v dd = 2.5v fosc = 25 mhz, v dd = 5.5v hs + pll osc configuration fosc = 10 mhz, v dd = 5.5v d013 pic18cxx8 ? ? ? ? 50 50 ma ma hs osc configurations fosc = 25 mhz, v dd = 5.5v hs + pll osc configuration fosc = 10 mhz, v dd = 5.5v d014 pic18lcxx8 ? ? ? ? 48 tbd a a timer1 osc configuration f osc = 32 khz, v dd = 2.5v f osc = 32 khz, v dd = 2.5v, 25 c d014 pic18cxx8 ? ? ? ? tbd tbd a a oscb osc configuration f osc = 32 khz, v dd = 4.2v f osc = 32 khz, v dd = 4.2v, 25 c legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode or during a device reset without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. ? 2000 microchip technology inc. advanced information ds30475a-page 315 pic18cxx8 25.1 dc characteristics (cont ? d) pic18lcxx8 (industrial) standard operating conditions (unless otherwise stated) operating temperature-40 c t a +85 c for industrial pic18cxx8 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min typ max units conditions d020 i pd power-down current (3) pic18lcxx8 ? ? ? <2.5 ? ? 5 36 tbd a a a v dd = 2.5v, -40 c to +85 c v dd = 5.5v, -40 c to +85 c v dd = 2.5v, 25 c d020 pic18cxx8 ? ? <1 ? tbd 36 a a v dd = 4.2v, -40 c to +85 c v dd = 5.5v, -40 c to +85 c d020a ? ? tbd a v dd = 4.2v, 25 c d021b ? ? tbd ? tbd 42 a v dd = 4.2v, -40 c to +125 c v dd = 5.5v, -40 c to +125 c d022 ? i wdt module differential current pic18lcxx8 watchdog timer ? ? ? ? ? ? 12 25 tbd a a a v dd = 2.5v v dd = 5.5v v dd = 2.5v, 25 c d022 pic18cxx8 watchdog timer ? ? ? ? ? ? 25 tbd tbd a a a v dd = 5.5v, -40 c to +85 c v dd = 5.5v, -40 c to +125 c v dd = 4.2v, 25 c d022a ? i bor pic18lcxx8 brown-out reset ? ? ? ? 50 tbd a a v dd = 5.5v v dd = 2.5v, 25 c d022a pic18cxx8 brown-out reset ? ? ? ? ? ? 50 tbd tbd a a a v dd = 5.5v, -40 c to +85 c v dd = 5.5v, -40 c to +125 v dd = 4.2v, 25 c d022b ? i lvd pic18lcxx8 low voltage detect ? ? ? ? 50 tbd a a v dd = 2.5v v dd = 2.5v, 25 c d022b pic18cxx8 low voltage detect ? ? ? ? ? ? tbd tbd tbd a a a v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c v dd = 4.2v, 25 c d025 ? i oscb pic18lcxx8 timer1 oscillator ? ? ? ? 3 tbd a a v dd = 2.5v v dd = 2.5v, 25 c d025 pic18cxx8 timer1 oscillator ? ? ? ? ? ? tbd tbd tbd a a a v dd = 4.2v, -40 c to +85 c v dd = 4.2v, -40 c to +125 c v dd = 4.2v, 25 c legend: rows are shaded for improved readability. note 1: this is the limit to which v dd can be lowered in sleep mode or during a device reset without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd mclr = v dd ; wdt enabled/disabled as specified. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss , and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, ...). 4: for rc osc configuration, current through r ext is not included. the current through the resistor can be esti- mated by the formula ir = v dd /2r ext (ma) with r ext in kohm. pic18cxx8 ds30475a-page 316 advanced information ? 2000 microchip technology inc. 25.2 d c characteristics: pic18cxx8 ( industrial, extended) and pic18lcxx 8 ( industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 v ss v ss 0.2v dd 0.3v dd v v d032 mclr v ss 0.2v dd v d032a osc1 (in xt, hs and lp modes) and t1osi v ss 0.3v dd v d033 osc1(in rc mode) (1) v ss 0.2v dd v v ih input high voltage i/o ports: d040 with ttl buffer 0.25v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8v dd 0.7v dd v dd v dd v v d042 mclr 0.8v dd v dd v d042a osc1 (in xt, hs and lp modes) and t1osi 0.7v dd v dd v d043 osc1 (rc mode) (1) 0.9v dd v dd v v hys hysteresis of schmitt trigger inputs d050 tbd tbd v i il input leakage current (2,3) d060 i/o ports ? 1 av ss v pin v dd , pin at hi-impedance d061 mclr ? 5 avss v pin v dd d063 osc1 ? 5 avss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. ? 2000 microchip technology inc. advanced information ds30475a-page 317 pic18cxx8 25.2 dc characteristics: pic18cxx8 ( industrial, extended) and pic18lcxx 8 ( industrial) (cont ? d) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ device min max units conditions v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clko (rc mode) ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage (3) d090 i/o ports v dd - 0.7 ? vi oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd - 0.7 ? vi oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clko (rc mode) v dd - 0.7 ? vi oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd - 0.7 ? vi oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c v od open-drain high voltage d150 ? 7.5 v ra4 pin capacitive loading specs on output pins d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf in i 2 c mode note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. pic18cxx8 ds30475a-page 318 advanced information ? 2000 microchip technology inc. figure 25-3: low voltage detect characteristics table 25-1: low voltage detect characteristics v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software) standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended param no. symbol characteristic/ min max units conditions d420 v lvd lvd voltage lvdl<3:0> = 0100 2.5 2.66 v lvdl<3:0> = 0101 2.7 2.86 v lvdl<3:0> = 0110 2.8 2.98 v lvdl<3:0> = 0111 3.0 3.2 v lvdl<3:0> = 1000 3.3 3.52 v lvdl<3:0> = 1001 3.5 3.72 v lvdl<3:0> = 1010 3.6 3.84 v lvdl<3:0> = 1011 3.8 4.04 v lvdl<3:0> = 1100 4.0 4.26 v lvdl<3:0> = 1101 4.2 4.46 v lvdl<3:0> = 1110 4.5 4.78 v ? 2000 microchip technology inc. advanced information ds30475a-page 319 pic18cxx8 table 25-2: eprom programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +40 c param. no. sym characteristic min max units conditions internal program memory programming specs (note 1) d110 v pp voltage on mclr /v pp pin 12.75 13.25 v (note 2) d111 v ddp supply voltage during programming 4.75 5.25 v d112 i pp current into mclr /v pp pin ? 50 ma d113 i ddp supply current during programming ? 30 ma d114 t prog programming pulse width 100 1000 s terminated via internal/external interrupt or a reset d115 t erase eprom erase time device operation 3v device operation 3v 4 tbd ? ? hrs hrs note 1: these specifications are for the programming of the on-chip program memory eprom through the use of the table write instructions. the complete programming specifications can be found in: pic18cxx8 program- ming specifications (literature number ds39028). 2: the mclr /v pp pin may be kept in this range at times other than programming, but is not recommended. pic18cxx8 ds30475a-page 320 advanced information ? 2000 microchip technology inc. 25.3 ac (timing) characteristics 25.3.1 timing parameter symbology the timing parameter symbols have been created fol- lowing one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data-in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (hi-impedance) v valid l low z hi-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition ? 2000 microchip technology inc. advanced information ds30475a-page 321 pic18cxx8 25.3.2 timing conditions the temperature and voltages specified in table 25-3 apply to all timing specifications, unless otherwise noted. figure 25-4 specifies the load conditions for the timing specifications. table 25-3: temperature and voltage specifications - ac figure 25-4: load conditions for device timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +85 c for industrial -40 c t a +125 c for extended operating voltage v dd range as described in dc spec section 25.1. lc parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2 pic18cxx8 ds30475a-page 322 advanced information ? 2000 microchip technology inc. 25.3.3 timing diagrams and specifications figure 25-5: external clock timing table 25-4: external clock timing requirements osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a fosc external clkin frequency (1) dc 40 mhz xt osc dc 40 mhz hs osc 4 10 mhz hs + pll osc dc dc 40 40 khz mhz lp osc ec oscillator frequency (1) dc 4 mhz rc osc 0.1 4 mhz xt osc 4 25 mhz hs osc 4 10 mhz hs + pll osc 5 200 khz lp osc mode 1 tosc external clkin period (1) 250 ? ns xt and rc osc 40 ? ns hs osc 100 ? ns hs + pll osc 5 5 ? ? s ns lp osc ec oscillator period (1) 250 ? ns rc osc 250 10,000 ns xt osc 100 40 10,000 100 ns ns hs osc hs + pll osc 5 ? slp osc 2t cy instruction cycle time (1) 100 ? ns t cy = 4/f osc 3 tosl, to sh external clock in (osc1) high or low time 30 ? ns xt osc 2.5 ? ns lp osc 10 ? shs osc 4tosr, to sf external clock in (osc1) rise or fall time ? 20 ns xt osc ? 50 ns lp osc ? 7.5 ns hs osc note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at "min." values with an external clock applied to the osc1/clki pin. when an external clock input is used, the "max." cycle time limit is "dc" (no clock) for all devices. ? 2000 microchip technology inc. advanced information ds30475a-page 323 pic18cxx8 table 25-5: pll clock timing specification (v dd = 4.2v - 5.5v) param no. symbol characteristic min max units conditions 7t pll pll start-up time (lock time) ? 2ms ? clk clkout stability (jitter) using pll -2 +2 % pic18cxx8 ds30475a-page 324 advanced information ? 2000 microchip technology inc. figure 25-6: clkout and i/o timing table 25-6: clkout and i/o timing requirements note: refer to figure 25-4 for load conditions . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param. no. symbol characteristic min typ max units conditions 10 tosh2ckl osc1 to clkout ? 75 200 ns (1) 11 tosh2ckh osc1 to clkout ? 75 200 ns (1) 12 tckr clkout rise time ? 35 100 ns (1) 13 tckf clkout fall time ? 35 100 ns (1) 14 tckl2iov clkout to port out valid ?? 0.5t cy + 20 ns (1) 15 tiov2ckh port in valid before clkout 0.25t cy + 25 ?? ns (1) 16 tckh2ioi port in hold after clkout 0 ?? ns (1) 17 tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) pic18 c xx8 100 ?? ns 18a pic18 lc xx8 200 ?? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) 0 ?? ns 20 tior port output rise time pic18 c xx8 ? 10 25 ns 20a pic18 lc xx8 ?? 60 ns 21 tiof port output fall time pic18 c xx8 ? 10 25 ns 21a pic18 lc xx8 ?? 60 ns 22 ?? t inp int pin high or low time t cy ?? ns 23 ?? t rbp rb7:rb4 change int high or low time t cy ?? ns 24 ?? t rcp rc7:rc4 change int high or low time 20 ?? ns ?? these parameters are asynchronous events, not related to any internal clock edges. note 1: measurements are taken in rc mode where clko pin output is 4 x t osc . ? 2000 microchip technology inc. advanced information ds30475a-page 325 pic18cxx8 figure 25-7: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 25-8: brown-out reset timing table 25-7: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 tmcl mclr pulse width (low) 2 ?? s 31 t wdt watchdog timer time-out period (no prescaler) 71833ms 32 t ost oscillation start-up timer period 1024t osc ? 1024t osc ? t osc = osc1 period 33 t pwrt power up timer period 28 72 132 ms 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset ? 2 ? s 35 t bor brown-out reset pulse width 200 ?? sv dd b vdd (see d005) 36 t ivrst time for internal reference voltage to become stable ? 20 50 s v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 25-4 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal reference voltage internal reference voltage stable 36 pic18cxx8 ds30475a-page 326 advanced information ? 2000 microchip technology inc. figure 25-9: timer0 and timer1 external clock timings table 25-8: timer0 and timer1 external clock requirements note: refer to figure 25-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ? ns with prescaler 10 ? ns 41 tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ? ns with prescaler 10 ? ns 42 tt0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 n s or t cy + 40 n ? ns n = prescale value (1, 2, 4,..., 256) 45 tt1h t1cki high time synchronous, no prescaler 0.5t cy + 20 ? ns synchronous, with prescaler pic18 c xx8 10 ? ns pic18 lc xx8 25 ? ns asynchronous pic18 c xx8 30 ? ns pic18 lc xx8 50 ? ns 46 tt1l t1cki low time synchronous, no prescaler 0.5t cy + 5 ? ns synchronous, with prescaler pic18 c xx8 10 ? ns pic18 lc xx8 25 ? ns asynchronous pic18 c xx8 30 ? ns pic18 lc xx8 tbd tbd ns 47 tt1p t1cki input period synchronous greater of: 20 n s or t cy + 40 n ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ns ft1 t1cki oscillator input frequency range dc 50 khz 48 tcke2tmri delay from external t1cki clock edge to timer increment 2tosc 7tosc ? ? 2000 microchip technology inc. advanced information ds30475a-page 327 pic18cxx8 figure 25-10: capture/compare/pwm timings (ccp1 and ccp2) table 25-9: capture/compare/pwm requirements (ccp1 and ccp2) note: refer to figure 25-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param. no. symbol characteristic min max units conditions 50 tccl ccpx input low time no prescaler 0.5t cy + 20 ? ns with prescaler pic18 c xx8 10 ? ns pic18 lc xx8 20 ? ns 51 tcch ccpx input high time no prescaler 0.5t cy + 20 ? ns with prescaler pic18 c xx8 10 ? ns pic18 lc xx8 20 ? ns 52 tccp ccpx input period 3t cy + 40 n ? ns n = prescale value (1,4 or 16) 53 tccr ccpx output fall time pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 54 tccf ccpx output fall time pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns pic18cxx8 ds30475a-page 328 advanced information ? 2000 microchip technology inc. figure 25-11: parallel slave port timing (pic18c658 and pic18c858) table 25-10: parallel slave port requirements (pic18c658 and pic18c858) note: refer to figure 25-4 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param. no. symbol characteristic min max units conditions 62 tdtv2wrh data-in valid before wr or cs (setup time) 20 25 ? ? ns ns extended temp range 63 twrh2dti wr or cs to data-in invalid (hold time) pic18 c xx8 20 ? ns pic18 lc xx8 35 ? ns 64 trdl2dtv rd and cs to data-out valid ? ? 80 90 ns ns extended temp range 65 trdh2dti rd or cs to data-out invalid 10 30 ns 66 tibfinh inhibit the ibf flag bit being cleared from wr or cs ? 3t cy ns ? 2000 microchip technology inc. advanced information ds30475a-page 329 pic18cxx8 figure 25-12: example spi master mode timing (cke = 0) table 25-11: example spi mode requirements (master mode, cke = 0) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit6 - - - - - -1 msb in lsb in bit6 - - - -1 note: refer to figure 25-4 for load conditions. param. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xx8 ? 50 ns pic18 lc xx8 ? 100 ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used. pic18cxx8 ds30475a-page 330 advanced information ? 2000 microchip technology inc. figure 25-13: example spi master mode timing (cke = 1) table 25-12: example spi mode requirements (master mode, cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit6 - - - - - -1 lsb in bit6 - - - -1 lsb note: refer to figure 25-4 for load conditions. param. no. symbol characteristic min max units conditions 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, ts c l 2 d i l hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 78 tscr sck output rise time (master mode) pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xx8 ? 50 ns pic18 lc xx8 ? 100 ns 81 tdov2sch, tdov2scl sdo data output setup to sck edge t cy ? ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used. ? 2000 microchip technology inc. advanced information ds30475a-page 331 pic18cxx8 figure 25-14: example spi slave mode timing (cke = 0) table 25-13: example spi mode requirements (slave mode timing (cke = 0)) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit6 - - - - - -1 msb in bit6 - - - -1 lsb in 83 note: refer to figure 25-4 for load conditions. parm. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 tdiv2sch, tdiv2scl setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xx8 ? 25 ns pic18 lc xx8 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 c xx8 ? 25 ns pic18 lc xx8 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xx8 ? 50 ns pic18 lc xx8 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used. pic18cxx8 ds30475a-page 332 advanced information ? 2000 microchip technology inc. figure 25-15: example spi slave mode timing (cke = 1) table 25-14: example spi slave mode requirements (cke = 1) ss sck (ckp = 0) sck (ckp = 1) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit6 - - - - - -1 lsb 77 msb in bit6 - - - -1 lsb in 80 83 note: refer to figure 25-4 for load conditions. parm. no. symbol characteristic min max units conditions 70 tssl2sch, tssl2scl ss to sck or sck input t cy ? ns 71 tsch sck input high time (slave mode) continuous 1.25t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 tscl sck input low time (slave mode) continuous 1.25t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte1 to the 1st clock edge of byte2 1.5t cy + 40 ? ns (note 2) 74 tsch2dil, tscl2dil hold time of sdi data input to sck edge 100 ? ns 75 tdor sdo data output rise time pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 76 tdof sdo data output fall time ? 25 ns 77 tssh2doz ss to sdo output hi-impedance 10 50 ns 78 tscr sck output rise time (master mode) pic18 c xx8 ? 25 ns pic18 lc xx8 ? 45 ns 79 tscf sck output fall time (master mode) ? 25 ns 80 tsch2dov, tscl2dov sdo data output valid after sck edge pic18 c xx8 ? 50 ns pic18 lc xx8 ? 100 ns 82 tssl2dov sdo data output valid after ss edge pic18 c xx8 ? 50 ns pic18 lc xx8 ? 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter #s 71a and 72a are used. ? 2000 microchip technology inc. advanced information ds30475a-page 333 pic18cxx8 figure 25-16: i 2 c bus start/stop bits timing table 25-15: i 2 c bus start/stop bits requirements (slave mode) note: refer to figure 25-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 parm. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? pic18cxx8 ds30475a-page 334 advanced information ? 2000 microchip technology inc. figure 25-17: i 2 c bus data timing table 25-16: i 2 c bus data requirements (slave mode) note: refer to figure 25-4 for load conditions . 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18cxx8 must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18cxx8 must operate at a minimum of 10 mhz ssp module 1.5t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18cxx8 must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18cxx8 must operate at a minimum of 10 mhz ssp module 1.5t cy ? ns 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1cb 300 ns cb is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ?? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 cb bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement tsu;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. before the scl line is released, t r max. + tsu;dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification). ? 2000 microchip technology inc. advanced information ds30475a-page 335 pic18cxx8 figure 25-18: master ssp i 2 c bus start/stop bits timing waveforms table 25-17: master ssp i 2 c bus start/stop bits requirements note: refer to figure 25-4 for load conditions. 91 93 scl sda start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins. pic18cxx8 ds30475a-page 336 advanced information ? 2000 microchip technology inc. figure 25-19: master ssp i 2 c bus data timing table 25-18: master ssp i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 1 mhz mode ( 1 ) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns cb is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 1 mhz mode ( 1 ) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode ( 1 ) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode ( 1 ) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode ( 1 ) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode ( 1 ) ?? ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmis- sion can start 400 khz mode 1.3 ? ms 1 mhz mode ( 1 ) tbd ? ms d102 cb bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line. before the scl line is released, parameter #102+ parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode). note: refer to figure 25-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out ? 2000 microchip technology inc. advanced information ds30475a-page 337 pic18cxx8 figure 25-20: usart synchronous transmission (master/slave) timing table 25-19: usart synchronous transmission requirements note: refer to figure 25-4 for load conditions. 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin param. no. symbol characteristic min max units conditions 120 tckh2dtv sync xmit (m aster & s lave ) clock high to data-out valid pic18 c xx8 ? 40 ns pic18 lc xx8 ? 100 ns 121 tckrf clock out rise time and fall time (master mode) pic18 c xx8 ? 20 ns pic18 lc xx8 ? 50 ns 122 tdtrf data-out rise time and fall time pic18 c xx8 ? 20 ns pic18 lc xx8 ? 50 ns pic18cxx8 ds30475a-page 338 advanced information ? 2000 microchip technology inc. figure 25-21: usart synchronous receive (master/slave) timing table 25-20: usart synchronous receive requirements note: refer to figure 25-4 for load conditions. 125 126 rc6/tx/ck rc7/rx/dt pin pin param. no. symbol characteristic min max units conditions 125 tdtv2ckl sync rcv (m aster & s lave ) data-hold before ck (dt hold time) 10 ? ns 126 tckl2dtl data-hold after ck (dt hold time) 15 ? ns ? 2000 microchip technology inc. advanced information ds30475a-page 339 pic18cxx8 table 25-21: a/d converter characteristics: pic18cxx8 (industrial, extended) pic18lcxx8 (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? ? ? 10 tbd bit bit v ref = v dd 3.0v v ref = v dd < 3.0v a03 e il integral linearity error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a04 e dl differential linearity error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a05 e fs full scale error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a06 e off offset error ? ? ? ? <1 tbd lsb lsb v ref = v dd 3.0v v ref = v dd < 3.0v a10 ? monotonicity guaranteed ( 3 ) ? v ss v ain v ref a20 v ref reference voltage (v refh - v refl ) 0v ?? v a20a 3v ?? v for 10-bit resolution a21 v refh reference voltage high av ss ? av dd + 0.3v v a22 v refl reference voltage low av ss - 0.3v ? av dd v a25 v ain analog input voltage av ss - 0.3v ? v ref + 0.3v v a30 z ain recommended impedance of analog voltage source ?? 10.0 k ? a40 i ad a/d conversion current (v dd ) pic18 c xx8 ? 180 ? a average current consumption when a/d is on (1) . pic18 lc xxx ? 90 ? a a50 i ref v ref input current (2) 10 ? ? ? 1000 10 a a during v ain acquisition. based on differential of v hold to v ain . to charge c hold see section 18.0. during a/d conversion cycle. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. v ref current is from ra2/an2/v ref - and ra3/an3/v ref + pins or av dd and av ss pins, whichever is selected as reference input. 2: v ss v ain v ref 3: the a/d conversion result either increases or remains constant as the analog input increases. pic18cxx8 ds30475a-page 340 advanced information ? 2000 microchip technology inc. figure 25-22: a/d conversion timing table 25-22: a/d conversion requirements param no. sym- bol characteristic min max units conditions 130 t ad a/d clock period pic18 c xx8 1.6 20 (5) st osc based, v ref 3.0v pic18 lc xx8 3.0 20 (5) st osc based, v ref full range pic18 c xx8 2.0 6.0 s a/d rc mode pic18 lc xx8 3.0 9.0 s a/d rc mode 131 t cnv conversion time (not including acquisition time) (1) 11 12 t ad 132 t acq acquisition time (3) 15 10 ? ? s s -40 c te m p 125 c 0 c te m p 125 c 135 t swc switching time from convert sample ? (note 4) 136 t amp amplifier settling time (note 2) 1 ? s this may be used if the ? new ? input voltage has not changed by more than 1 lsb (i.e., 5 mv @ 5.12v) from the last sampled voltage (as stated on c hold ). note 1: adres register may be read on the following t cy cycle. 2: see section 18.0 for minimum conditions, when input voltage has changed more than 1 lsb. 3: the time for the holding capacitor to acquire the ? new ? input voltage, when the voltage changes full scale after the conversion (av dd to av ss , or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 ? . 4: on the next q4 cycle of the device clock. 5: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data note 2 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts.this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy ? 2000 microchip technology inc. advanced information ds30475a-page 341 pic18cxx8 26.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time. pic18cxx8 ds30475a-page 342 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 343 pic18cxx8 27.0 packaging information 27.1 package marking informatio n 68-lead plcc example 64-lead tqfp example * standard otp marking consists of microchip part number, year code, week code and traceability code. for otp marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer specific information* yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. 80-lead tqfp example xxxxxxxxxx yywwnnn xxxxxxxxxx xxxxxxxxxx 0017017 pic18c658-i/pt xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn pic18c658-i/l 0017017 xxxxxxxxxxxx yywwnnn xxxxxxxxxxxx 0017017 pic18c858-i/pt pic18cxx8 ds30475a-page 344 advanced information ? 2000 microchip technology inc. package marking information (cont ? d) 84-lead plcc example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn pic18c858-i/l 0017017 ? 2000 microchip technology inc. advanced information ds30475a-page 345 pic18cxx8 64-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-085 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 significant characteristic pic18cxx8 ds30475a-page 346 advanced information ? 2000 microchip technology inc. 68-lead plastic leaded chip carrier (l) ? square (plcc) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b lower lead width 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 17 17 n1 pins per side 23.62 23.37 22.61 .930 .920 .890 d2 footprint length 23.62 23.37 22.61 .930 .920 .890 e2 footprint width 24.33 24.23 24.13 .958 .954 .950 d1 molded package length 24.33 24.23 24.13 .958 .954 .950 e1 molded package width 25.27 25.15 25.02 .995 .990 .985 d overall length 25.27 25.15 25.02 .995 .990 .985 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 68 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p b a3 a b1 32 d2 68 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 ch1 x 45 ch2 x 45 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-049 significant characteristic ? 2000 microchip technology inc. advanced information ds30475a-page 347 pic18cxx8 80-lead plastic thin quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-092 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 0.50 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .541 .551 .561 13.75 14.00 14.25 overall length d .541 .551 .561 13.75 14.00 14.25 molded package width e1 .463 .472 .482 11.75 12.00 12.25 molded package length d1 .463 .472 .482 11.75 12.00 12.25 pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 significant characteristic pic18cxx8 ds30475a-page 348 advanced information ? 2000 microchip technology inc. 84-lead plastic leaded chip carrier (l) ? square (plcc) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.53 0.51 0.33 .021 .020 .013 b lower lead width 0.81 0.74 0.66 .032 .029 .026 b1 upper lead width 0.33 0.27 0.20 .013 .011 .008 c lead thickness 17 17 n1 pins per side 23.62 23.37 22.61 .930 .920 .890 d2 footprint length 23.62 23.37 22.61 .930 .920 .890 e2 footprint width 24.33 24.23 24.13 .958 .954 .950 d1 molded package length 24.33 24.23 24.13 .958 .954 .950 e1 molded package width 25.27 25.15 25.02 .995 .990 .985 d overall length 25.27 25.15 25.02 .995 .990 .985 e overall width 0.25 0.13 0.00 .010 .005 .000 ch2 corner chamfer (others) 1.27 1.14 1.02 .050 .045 .040 ch1 corner chamfer 1 0.86 0.74 0.61 .034 .029 .024 a3 side 1 chamfer height 0.51 .020 a1 standoff a2 molded package thickness 4.57 4.39 4.19 .180 .173 .165 a overall height 1.27 .050 p pitch 68 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 c e2 2 d d1 n #leads=n1 e e1 1 p b a3 a b1 32 d2 68 a1 .145 .153 .160 3.68 3.87 4.06 .028 .035 0.71 0.89 ch1 x 45 ch2 x 45 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 ? (0.254mm) per side. jedec equivalent: mo-047 drawing no. c04-093 significant characteristic ? 2000 microchip technology inc. advanced information ds30475a-page 349 pic18cxx8 appendix a: data sheet revision history revision a this is a new data sheet. appendix b: device differences the differences between the pic18cxx8 devices listed in this data sheet are shown in table b-1. table b-1: device differences feature pic18c658 pic18c858 program memory (bytes) 32k 32k data memory (bytes) 1.5k 1.5k a/d channels 12 16 parallel slave port (psp) yes yes external memory capability no no package types tqfp 64-pin 80-pin plcc 68-pin 84-pin jcerpack 68-pin 84-pin pic18cxx8 ds30475a-page 350 advanced information ? 2000 microchip technology inc. appendix c: device migrations this section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a pic16c74a to a pic16c74b). not applicable appendix d: migrating from other picmicro devices this discusses some of the issues in migrating from other picmicro devices to the pic18cxxx family of devices. d.1 pic16cxxx to pic18cxxx see application note an716. d.2 pic17cxxx to pic18cxxx see application note an726. ? 2000 microchip technology inc. advanced information ds30475a-page 351 pic18cxx8 appendix e: development tool version requirements this lists the minimum requirements (software/firm- ware) of the specified development tool to support the devices listed in this data sheet. mplab-ide: version 5.11 mplab-sim: version 7.10 mplab-ice 2000: pic18cxx8 processor module: part number - pcm 18xb0 pic18cxx8 device adapter: socket part number 64-pin tqfp dvd18p2640 68-pin plcc dvd18xl680 80-pin tqfp dvd18pq800 84-pin plcc dvd18xl840 mplab-icd: not available promate ii: version 5.20 picstart plus: version 2.20 mpasm: version 2.50 mplab-c18: version 1.00 can-tool: not available at time of printing. note: please read all associated readme.txt files that are supplied with the develop- ment tools. these "read me" files will dis- cuss product support and any known limitations. pic18cxx8 ds30475a-page 352 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 353 pic18cxx8 index a a/d ................................................................................... 227 a/d converter flag (adif bit) ................................. 230 a/d converter interrupt, configuring ....................... 231 adcon0 register ............................................ 227, 229 adcon1 register ............................................ 227, 228 adcon2 register .................................................... 227 adres register .............................................. 227, 230 analog port pins, configuring .................................. 233 block diagram .......................................................... 230 block diagram, analog input model ......................... 231 configuring the module ............................................ 231 conversion clock (t ad ) ........................................... 233 conversion status (go/done bit) .......................... 230 conversions ............................................................. 234 converter characteristics ........................................ 339 converter characteristics .......................................... 318 effects of a reset .................................................. 250 equations ................................................................. 232 operation during sleep ......................................... 250 sampling requirements ........................................... 232 sampling time ......................................................... 232 special event trigger (ccp) ............................ 130, 234 timing diagram ........................................................ 340 absolute maximum ratings ............................................. 311 acknowledge error ........................................................... 223 adcon0 register .................................................... 227, 229 go/done bit ........................................................... 230 adcon1 register .................................................... 227, 228 adcon2 register ............................................................ 227 addlw ............................................................................ 267 addwf ............................................................................ 267 addwfc ......................................................................... 268 adres register ...................................................... 227, 230 aks .................................................................................. 156 analog-to-digital converter. see a/d andlw ............................................................................ 268 andwf ............................................................................ 269 assembler mpasm assembler .................................................. 305 b baud rate generator ....................................................... 153 bcf .................................................................................. 270 bf .................................................................................... 156 bit error ............................................................................ 223 bit timing ......................................................................... 218 bit timing configuration registers .................................. 222 block diagrams baud rate generator ............................................... 153 comparator i/o operating modes ............................ 238 portk ..................................................................... 108 ssp (spi mode) ....................................................... 141 timer3 ...................................................................... 124 bor. see brown-out reset brg ................................................................................. 153 brown-out reset (bor) ............................................. 30, 251 timing diagram ........................................................ 325 bsf .......................... 269, 270, 271, 272, 273, 275, 276, 291 btfsc ............................................................................. 274 btfss ............................................................................. 274 btg ................................................................................. 275 bus activity wake-up interrupt ........................................ 225 bus collision during a restart condition ................... 165 bus collision during a start condition ........................ 163 bus collision during a stop condition .......................... 166 bus off ............................................................................. 226 c call ................................................................................ 276 can buffers and protocol engine block diagram ........... 184 capture (ccp module) .................................................... 128 block diagram ......................................................... 129 ccp pin configuration ............................................ 128 ccpr1h:ccpr1l registers .................................. 128 changing between capture prescalers .................. 129 software interrupt .................................................... 129 timer1 mode selection ............................................ 128 capture/compare/pwm (ccp) ....................................... 127 capture mode. see capture ccp1 ....................................................................... 128 ccpr1h register ........................................... 128 ccpr1l register ............................................ 128 ccp2 ....................................................................... 128 ccpr2h register ........................................... 128 ccpr2l register ............................................ 128 compare mode. see compare interaction of two ccp modules ............................. 128 pwm mode. see pwm timer resources ..................................................... 128 timing diagram ....................................................... 327 clocking scheme ............................................................... 45 clrf ....................................................................... 277, 295 clrwdt ......................................................................... 277 code examples loading the sspbuf register ................................ 142 code protection ....................................................... 251, 259 comf .............................................................................. 278 comparator interrupts ...................................................... 241 comparator operation ..................................................... 239 comparator reference .................................................... 239 compare (ccp module) .................................................. 130 block diagram ......................................................... 130 ccp pin configuration ............................................ 130 ccpr1h:ccpr1l registers .................................. 130 software interrupt .................................................... 130 special event trigger ...................... 119, 125, 130, 234 timer1 mode selection ............................................ 130 configuration bits ............................................................ 251 configuration mode ......................................................... 210 configuring the voltage reference .................................. 243 cpfseq .......................................................................... 278 cpfsgt .......................................................................... 279 cpfslt ........................................................................... 279 crc error ........................................................................ 223 cvrcon register ........................................................... 243 pic18cxx8 ds30475a-page 354 advanced information ? 2000 microchip technology inc. d data memory ...................................................................... 48 general purpose registers ........................................ 48 special function registers ........................................ 48 daw ................................................................................. 280 dc characteristics ........................... 313, 314, 315, 316, 317 decf ............................................................................... 280 decfsnz ........................................................................ 281 decfsz ........................................................................... 281 device differences ........................................................... 349 device functionality ......................................................... 184 direct addressing ............................................................... 62 e electrical characteristics .................................................. 311 errata ................................................................................... 7 error detection ................................................................. 223 error interrupt ................................................................... 226 error modes ..................................................................... 224 error modes and error counters ...................................... 223 error states ...................................................................... 223 f filter/mask truth table .................................................... 216 firmware instructions ....................................................... 261 form error ........................................................................ 223 g general call address sequence ...................................... 150 general call address support ......................................... 150 goto ............................................................................... 282 h hard synchronization ....................................................... 220 i i/o ports ............................................................................. 89 i 2 c (ssp module) ............................................................. 147 ack pulse ................................................ 147, 148, 149 addressing ............................................................... 148 block diagram .......................................................... 147 read/write bit information (r/w bit) ............... 148, 149 reception ................................................................. 149 serial clock (rc3/sck/scl) ................................... 149 slave mode .............................................................. 147 timing diagram, data .............................................. 334 timing diagram, start/stop bits ............................... 333 transmission ............................................................ 149 i 2 c master mode reception ............................................. 156 i 2 c master mode restart condition ................................. 155 i 2 c module acknowledge sequence timing ................................ 159 baud rate generator ............................................... 153 brg block diagram ................................................. 153 brg reset due to sda collision ............................. 164 brg timing ............................................................. 153 bus collision acknowledge .................................................... 162 restart condition ............................................. 165 restart condition timing (case1) .................... 165 restart condition timing (case2) .................... 165 start condition ............................................. 163 start condition timing ............................. 163, 164 stop condition ............................................... 166 stop condition timing (case1) ..................... 166 stop condition timing (case2) ..................... 166 transmit timing ............................................... 162 bus collision timing ................................................. 162 clock arbitration ...................................................... 161 clock arbitration timing (master transmit) ............. 161 general call address support ................................. 150 master mode 7-bit reception timing ........................ 158 master mode operation ........................................... 152 master mode start condition ................................... 154 master mode transmission ..................................... 156 master mode transmit sequence ............................ 152 multi-master mode ................................................... 162 repeat start condition timing .............................. 155 stop condition receive or transmit timing ........... 160 stop condition timing ............................................ 159 waveforms for 7-bit reception ................................ 149 waveforms for 7-bit transmission ........................... 149 id locations ............................................................. 251, 259 incf ................................................................................ 282 incfsnz ......................................................................... 283 incfsz ............................................................................ 283 in-circuit serial programming (icsp) ...................... 251, 259 indirect addressing ............................................................ 62 fsr register ............................................................. 61 information processing time ........................................... 219 initiating message transmission ..................................... 211 instruction cycle ................................................................ 45 instruction flow/pipelining ................................................. 46 instruction format ............................................................ 263 instruction set .................................................................. 261 addlw .................................................................... 267 addwf .................................................................... 267 addwfc ................................................................. 268 andlw .................................................................... 268 andwf .................................................................... 269 bcf ......................................................................... 270 bsf .................. 269, 270, 271, 272, 273, 275, 276, 291 btfsc ..................................................................... 274 btfss ..................................................................... 274 btg ......................................................................... 275 call ........................................................................ 276 clrf ............................................................... 277, 295 clrwdt ................................................................. 277 comf ...................................................................... 278 cpfseq .................................................................. 278 cpfsgt .................................................................. 279 cpfslt ................................................................... 279 daw ........................................................................ 280 decf ....................................................................... 280 decfsnz ................................................................ 281 decfsz .................................................................. 281 goto ...................................................................... 282 incf ........................................................................ 282 incfsnz ................................................................. 283 incfsz .................................................................... 283 iorlw ..................................................................... 284 iorwf ..................................................................... 284 movfp .................................................................... 286 movlb .................................................................... 285 movlr ............................................................ 285, 286 movlw ................................................................... 287 movwf ................................................................... 287 mullw .................................................................... 288 mulwf .................................................................... 288 negw ..................................................................... 289 nop ......................................................................... 289 retfie ............................................................ 291, 292 retlw .................................................................... 292 ? 2000 microchip technology inc. advanced information ds30475a-page 355 pic18cxx8 return .................................................................. 293 rlcf ........................................................................ 293 rlncf ..................................................................... 294 rrcf ....................................................................... 294 rrncf .................................................................... 295 sleep ..................................................................... 296 sublw .................................................................... 297 subwf ............................................................ 297, 298 subwfb .................................................................. 299 swapf .................................................................... 300 tablrd ................................................................... 301 tablwt .................................................................. 302 tstfsz ................................................................... 303 xorlw .................................................................... 303 xorwf .................................................................... 304 summary table ........................................................ 264 int interrupt (rb0/int). see interrupt sources intcon register rbif bit ...................................................................... 91 inter-integrated circuit. see i 2 c interrupt acknowledge ..................................................... 226 interrupt sources ....................................................... 75, 251 a/d conversion complete ....................................... 231 capture complete (ccp) ......................................... 129 compare complete (ccp) ....................................... 130 interrupt-on-change (rb7:rb4 ) ............................... 91 rb0/int pin, external ................................................ 88 ssp receive/transmit complete ............................ 135 tmr0 overflow ........................................................ 116 tmr1 overflow ................................................ 117, 119 tmr2 to pr2 match ................................................ 122 tmr2 to pr2 match (pwm) ............................ 121, 132 tmr3 overflow ................................................ 123, 125 usart receive/transmit complete ....................... 167 interrupts .......................................................................... 225 interrupts, enable bits ccp1 enable (ccp1ie bit) ...................................... 129 interrupts, flag bits a/d converter flag (adif bit) ................................. 230 ccp1 flag (ccp1if bit) .......................... 128, 129, 130 interrupt on change (rb7:rb4) flag (rbif bit) ........ 91 iorlw ............................................................................. 284 iorwf ............................................................................. 284 k k ee l oq evaluation and programming tools ................... 308 l lengthening a bit period .................................................. 221 listen only mode ............................................................. 210 loopback mode ............................................................... 211 m memory organization data memory ............................................................. 48 program memory ....................................................... 41 message acceptance filter .............................................. 217 message acceptance filters and masks ......................... 216 message reception ......................................................... 213 message reception flowchart ......................................... 215 movfp ............................................................................ 286 movlb ............................................................................ 285 movlr .................................................................... 285, 286 movlw ........................................................................... 287 movwf ........................................................................... 287 mplab integrated development environment software ..................................................... 305 mullw ............................................................................ 288 multi-master mode ........................................................... 162 multiply examples 16 x 16 routine ......................................................... 72 16 x 16 signed routine ............................................. 73 8 x 8 routine ............................................................. 72 8 x 8 signed routine ................................................. 72 mulwf ............................................................................ 288 n negw ............................................................................. 289 nop ................................................................................. 289 normal mode ................................................................... 210 o option_reg register ..................................................... 64 ps2:ps0 bits ........................................................... 115 psa bit .................................................................... 115 t0cs bit .................................................................. 115 t0se bit .................................................................. 115 osccon ........................................................................... 25 osccon register ............................................................. 25 oscillator configuration ............................................. 21, 251 hs .............................................................................. 21 hs + pll ................................................................... 21 lp .............................................................................. 21 rc ....................................................................... 21, 23 rcio .......................................................................... 21 xt .............................................................................. 21 oscillator tolerance ......................................................... 222 oscillator, timer1 ............................................. 117, 119, 123 oscillator, timer3 ............................................................. 125 oscillator, wdt ................................................................ 255 overview .......................................................................... 183 p packaging ........................................................................ 343 parallel slave port (psp) ........................................... 95, 109 block diagram ......................................................... 109 re0/rd ................................................................... 109 re1/wr ................................................................... 109 re2/cs .................................................................... 109 read waveforms ..................................................... 111 select (pspmode bit) ...................................... 95, 109 timing diagram ....................................................... 328 write waveforms ..................................................... 111 phase buffer segments ................................................... 219 picdem 1 low cost picmicro demo board ................... 307 picdem 2 low cost pic16cxx demo board ................ 307 picdem 3 low cost pic16cxxx demo board .............. 308 picstart plus entry level development system ......... 307 pin functions a vdd .......................................................................... 20 a vss .......................................................................... 20 mclr /v pp ................................................................. 12 osc1/clki ................................................................ 12 osc2/clko .............................................................. 12 ra0/an0 .................................................................... 13 ra1/an1 .................................................................... 13 ra2/an2/v ref - ......................................................... 13 ra3/an3/v ref + ........................................................ 13 ra4/t0cki ................................................................ 13 ra5/an4/ss /lvdin .................................................. 13 ra6 ............................................................................ 13 rb0/int0 ................................................................... 14 pic18cxx8 ds30475a-page 356 advanced information ? 2000 microchip technology inc. rb1/int1 ................................................................... 14 rb2/int2 ................................................................... 14 rb3/int3 ................................................................... 14 rb4 ............................................................................ 14 rb5 ............................................................................ 14 rb6 ............................................................................ 14 rb7 ............................................................................ 14 rc0/t1oso/t1cki ................................................... 15 rc1/t1osi ................................................................ 15 rc2/ccp1 ................................................................. 15 rc3/sck/scl ........................................................... 15 rc4/sdi/sda ............................................................ 15 rc5/sdo ................................................................... 15 rc6/tx/ck ................................................................ 15 rc7/rx/dt ................................................................ 15 rd0/ad0 .................................................................... 16 rd0/psp0 .................................................................. 16 rd1/ad1 .................................................................... 16 rd1/psp1 .................................................................. 16 rd2/ad2 .................................................................... 16 rd2/psp2 .................................................................. 16 rd3/ad3 .................................................................... 16 rd3/psp3 .................................................................. 16 rd4/ad4 .................................................................... 16 rd4/psp4 .................................................................. 16 rd5/ad5 .................................................................... 16 rd5/psp5 .................................................................. 16 rd6/ad6 .................................................................... 16 rd6/psp6 .................................................................. 16 rd7/ad7 .................................................................... 16 rd7/psp7 .................................................................. 16 re0/ale .................................................................... 17 re0/rd ...................................................................... 17 re1/oe ...................................................................... 17 re1/wr ..................................................................... 17 re2/cs ...................................................................... 17 re2/wrl ................................................................... 17 re3/wrh .................................................................. 17 re4 ............................................................................ 17 re5 ............................................................................ 17 re6 ............................................................................ 17 re7/ccp2 ................................................................. 17 rf0/an5 .................................................................... 18 rf1/an6 .................................................................... 18 rf2/an7 .................................................................... 18 rf3/an8 .................................................................... 18 rf4/an9 .................................................................... 18 rf5/an10 .................................................................. 18 rf6/an11 .................................................................. 18 rf7 ............................................................................ 18 rg0/cantx1 ............................................................ 19 rg1/cantx2 ............................................................ 19 rg2/canrx .............................................................. 19 rg3 ............................................................................ 19 rg4 ............................................................................ 19 rh0/a16 .................................................................... 19 rh1/a17 .................................................................... 19 rh2/a18 .................................................................... 19 rh3/a19 .................................................................... 19 rh4/an12 .................................................................. 19 rh5/an13 .................................................................. 19 rh6/an14 .................................................................. 19 rh7/an15 .................................................................. 19 rj0/ad8 ..................................................................... 20 rj1/ad9 ..................................................................... 20 rj2/ad10 ................................................................... 20 rj3/ad11 ................................................................... 20 rk0 ............................................................................ 20 rk1 ............................................................................ 20 rk2 ............................................................................ 20 rk3 ............................................................................ 20 v dd ............................................................................ 20 v ss ............................................................................ 20 pointer, fsr ...................................................................... 61 por. see power-on reset porta initialization ................................................................ 89 porta register ........................................................ 89 ra3:ra0 and ra5 port pins ..................................... 89 ra4/t0cki pin .......................................................... 90 trisa register .......................................................... 89 portb initialization ................................................................ 91 portb register ........................................................ 91 rb0/int pin, external ................................................ 88 rb3:rb0 port pins .................................................... 91 rb7:rb4 interrupt on change flag (rbif bit) .......... 91 rb7:rb4 port pins .................................................... 91 trisb register .......................................................... 91 portc block diagram ........................................................... 93 initialization ................................................................ 93 portc register ........................................................ 93 rc3/sck/scl pin ................................................... 149 rc7/rx/dt pin ........................................................ 169 trisc register .................................................. 93, 167 portd ............................................................................ 109 block diagram ........................................................... 95 initialization ................................................................ 95 parallel slave port (psp) function ............................ 95 portd register ........................................................ 95 trisd register .......................................................... 95 porte block diagram ........................................................... 97 initialization ................................................................ 97 porte register ........................................................ 97 psp mode select (pspmode bit) .................... 95, 109 re0/rd ................................................................... 109 re1/wr ................................................................... 109 re2/cs .................................................................... 109 trise register .......................................................... 97 portf block diagram ........................................................... 99 block diagram of rf7 pin ....................................... 100 c1out, c2out ........................................................ 99 initialization ................................................................ 99 portf register ........................................................ 99 rf6/rf3 and rf0 pins block diagram ................... 100 trisf ........................................................................ 99 portg initialization .............................................................. 101 portg .................................................................... 101 rg0/cantx0 pin block diagram ............................ 101 rg1/cantx1 pin block diagram ............................ 102 rg2 pin block diagram ........................................... 102 rg4/rg3 pins block diagram ................................. 102 trisg ...................................................................... 101 porth initialization .............................................................. 104 porth .................................................................... 104 rh3/rh0 pins block diagram ................................. 104 rh7/rh4 pins block diagram ................................. 104 trish ...................................................................... 104 ? 2000 microchip technology inc. advanced information ds30475a-page 357 pic18cxx8 portj initialization .............................................................. 106 portj ..................................................................... 106 trisj ....................................................................... 106 portj block diagram ..................................................... 106 portk initialization .............................................................. 108 portk ..................................................................... 108 trisk ...................................................................... 108 postscaler, wdt assignment (psa bit) .............................................. 115 rate select (ps2:ps0 bits) ..................................... 115 switching between timer0 and wdt ...................... 115 power-down mode. see sleep power-on reset (por) .............................................. 30, 251 oscillator start-up timer (ost) ......................... 30, 251 power-up timer (pwrt) ................................... 30, 251 time-out sequence .................................................... 31 time-out sequence on power-up ........................ 32, 33 timing diagram ........................................................ 325 prescaler, capture ........................................................... 129 prescaler, timer0 ............................................................. 115 assignment (psa bit) .............................................. 115 rate select (ps2:ps0 bits) ..................................... 115 switching between timer0 and wdt ...................... 115 prescaler, timer1 ............................................................. 118 prescaler, timer2 ............................................................. 132 pro mat ? ii universal programmer ............................... 307 program counter pcl register .............................................................. 45 pclath register ...................................................... 45 program memory ............................................................... 41 program verification ........................................................ 259 programmable ................................................................. 251 programming time segments ......................................... 222 programming, device instructions ................................... 261 propagation segment ...................................................... 219 pspcon register pspmode bit .................................................... 95, 109 pwm (ccp module) ........................................................ 132 block diagram .......................................................... 132 ccpr1h:ccpr1l registers ................................... 132 duty cycle ................................................................ 132 example frequencies/resolutions .......................... 133 output diagram ........................................................ 132 period ....................................................................... 132 setup for pwm operation ........................................ 133 tmr2 to pr2 match ........................................ 121, 132 q q-clock ............................................................................ 132 r ram. see data memory rcsta register spen bit .................................................................. 167 receive buffers ................................................................ 213 receive buffers diagram ................................................. 214 receive interrupt .............................................................. 225 receive message buffering ............................................. 213 receiver error passive .................................................... 226 receiver overrun ............................................................. 226 receiver warning ............................................................ 226 register file ....................................................................... 48 registers sspstat ................................................................ 136 t3con diagram ........................................................... 123 section ............................................................ 123 reset ....................................................................... 29, 251 timing diagram ....................................................... 325 resynchronization ........................................................... 220 retfie .................................................................... 291, 292 retlw ............................................................................ 292 return .......................................................................... 293 revision history ............................................................... 349 rlcf ............................................................................... 293 rlncf ............................................................................. 294 rrcf ............................................................................... 294 rrncf ............................................................................ 295 s sample point ................................................................... 219 sci. see usart sck ................................................................................. 141 sdi ................................................................................... 141 sdo ................................................................................. 141 serial clock, sck ............................................................ 141 serial communication interface. see usart serial data in, sdi ........................................................... 141 serial data out, sdo ...................................................... 141 serial peripheral interface. see spi shortening a bit period .................................................... 221 simplified block diagram of on-chip reset circuit ........... 29 slave select synchronization .......................................... 144 slave select, ss .............................................................. 141 sleep ............................................................. 251, 257, 296 software simulator (mplab-sim) ................................... 306 special event trigger. see compare special features of the cpu ................................... 247, 251 special function registers ................................................ 48 spi master mode ............................................................ 143 serial clock ............................................................. 141 serial data in ........................................................... 141 serial data out ........................................................ 141 slave select ............................................................. 141 spi clock ................................................................. 143 spi mode ................................................................. 141 spi module slave mode .............................................................. 144 slave select synchronization .................................. 144 slave synch timing ................................................. 144 slave timing with cke = 0 ...................................... 145 slave timing with cke = 1 ...................................... 145 ss .................................................................................... 141 ssp ................................................................................. 135 block diagram (spi mode) ...................................... 141 i 2 c mode. see i 2 c spi mode ................................................................. 141 spi mode. see spi sspbuf .................................................................. 143 sspcon1 ............................................................... 138 sspcon2 ............................................................... 140 sspsr .................................................................... 143 sspstat ................................................................ 136 tmr2 output for clock shift ............................ 121, 122 ssp module spi master mode ..................................................... 143 spi slave mode ....................................................... 144 sspcon1 ....................................................................... 138 sspcon2 ....................................................................... 140 pic18cxx8 ds30475a-page 358 advanced information ? 2000 microchip technology inc. sspov ............................................................................. 156 sspstat ......................................................................... 136 sspstat register r/w bit ............................................................. 148, 149 stuff error ......................................................................... 223 sublw ............................................................................ 297 subwf .................................................................... 297, 298 subwfb .......................................................................... 299 swapf ............................................................................ 300 synchronization ................................................................ 220 synchronization rules ..................................................... 220 synchronization segment ................................................ 219 synchronous serial port. see ssp t tablrd ........................................................................... 301 tablwt ........................................................................... 302 time quanta .................................................................... 219 timer modules timer3 block diagram .................................................. 124 timer0 .............................................................................. 113 clock source edge select (t0se bit) ...................... 115 clock source select (t0cs bit) ............................... 115 overflow interrupt .................................................... 116 prescaler. see prescaler, timer0 timing diagram ........................................................ 326 timer1 .............................................................................. 117 block diagram .......................................................... 118 oscillator .......................................................... 117, 119 overflow interrupt ............................................ 117, 119 prescaler. see prescaler, timer1 special event trigger (ccp) ............................ 119, 130 timing diagram ........................................................ 326 tmr1h register ...................................................... 117 tmr1l register ....................................................... 117 tmr3l register ....................................................... 123 timer2 block diagram .......................................................... 122 postscaler. see postscaler, timer2 pr2 register .................................................... 121, 132 prescaler. see prescaler, timer2 ssp clock shift ................................................ 121, 122 tmr2 register ......................................................... 121 tmr2 to pr2 match interrupt .................. 121, 122, 132 timer3 .............................................................................. 123 oscillator .......................................................... 123, 125 overflow interrupt ............................................ 123, 125 special event trigger (ccp) .................................... 125 tmr3h register ...................................................... 123 timing diagrams acknowledge sequence timing ............................... 159 baud rate generator with clock arbitration ............ 153 brg reset due to sda collision ............................ 164 bus collision start condition timing ................................. 163 bus collision during a restart condition (case 1) ................................................................... 165 bus collision during a restart condition (case2) .................................................................... 165 bus collision during a start condition (scl = 0) 164 bus collision during a stop condition ................... 166 bus collision for transmit and acknowledge ........... 162 i 2 c bus data ............................................................ 336 i 2 c master mode first start bit timing ...................... 154 i 2 c master mode reception timing .......................... 158 i 2 c master mode transmission timing ..................... 157 master mode transmit clock arbitration ................. 161 repeat start condition ............................................ 155 slave synchronization ............................................. 144 slow rise time .......................................................... 33 spi mode timing (master mode) spi mode master mode timing diagram ......................... 143 spi mode timing (slave mode with cke = 0) ......... 145 spi mode timing (slave mode with cke = 1) ......... 145 stop condition receive or transmit ........................ 160 time-out sequence on power-up .............................. 32 usart asynchronous master transmission .......... 174 usart asynchronous reception ............................ 176 usart synchronous reception ............................. 179 usart synchronous transmission ........................ 178 wake-up from sleep via interrupt .......................... 258 timing diagrams and specifications ............................... 322 a/d conversion ........................................................ 340 brown-out reset (bor) ........................................... 325 capture/compare/pwm (ccp) ............................... 327 clkout and i/o ..................................................... 324 external clock .......................................................... 322 i 2 c bus data ............................................................ 334 i 2 c bus start/stop bits ...................................... 333 oscillator start-up timer (ost) ............................... 325 parallel slave port (psp) ......................................... 328 power-up timer (pwrt) ......................................... 325 reset ....................................................................... 325 timer0 and timer1 .................................................. 326 usart synchronous receive ( master/slave) ....... 338 usart synchronous transmission ( master/slave) 337 watchdog timer (wdt) ........................................... 325 transmit interrupt ............................................................ 225 transmit message aborting ............................................. 211 transmit message buffering ............................................ 211 transmit message buffers ............................................... 211 transmit message flowchart ............................................ 212 transmit message priority ............................................... 211 transmitter error passive ................................................ 226 transmitter warning ........................................................ 226 trise register .................................................................. 97 tstfsz ........................................................................... 303 txsta register brgh bit ................................................................. 169 u universal synchronous asynchronous receiver transmitter. see usart usart ............................................................................. 167 asynchronous mode ................................................ 173 master transmission ....................................... 174 receive block diagram ................................... 175 reception ........................................................ 176 transmit block diagram .................................. 173 baud rate generator (brg) ................................... 169 baud rate error, calculating ........................... 169 baud rate formula ......................................... 169 high baud rate select (brgh bit) ................. 169 sampling .......................................................... 169 serial port enable (spen bit) ................................. 167 synchronous master mode ...................................... 177 reception ........................................................ 179 timing diagram, synchronous receive .......... 338 timing diagram, synchronous transmission .. 337 transmission ................................................... 178 synchronous slave mode ........................................ 180 ? 2000 microchip technology inc. advanced information ds30475a-page 359 pic18cxx8 w wake-up from sleep .............................................. 251, 257 timing diagram ........................................................ 258 watchdog timer (wdt) ........................................... 251, 255 block diagram .......................................................... 256 postscaler. see postscaler, wdt programming considerations .................................. 255 rc oscillator ............................................................ 255 time-out period ....................................................... 255 timing diagram ........................................................ 325 waveform for general call address sequence ............... 150 wcol .............................................................. 154, 156, 159 wcol status flag ........................................................... 154 www, on-line support ...................................................... 7 x xorlw ............................................................................ 303 xorwf ............................................................................ 304 pic18cxx8 ds30475a-page 360 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 361 pic18cxx8 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip ? s development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picmicro, picmaster, picstart, pro mate, k ee l oq , seeval, mplab and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. total endurance, icsp, in-circuit serial programming, filterlab, mxdev, microid, flex rom, fuzzy lab, mpasm, mplink, mplib, picdem, icepic and migratable memory are trademarks and sqtp is a service mark of microchip in the u.s.a. all other trademarks mentioned herein are the property of their respective companies. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user ? s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events 001024 pic18cxx8 ds30475a-page362 advanced information ? 2000 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30475a pic18cxx8 ? 2000 microchip technology inc. advanced information ds30475a-page 363 pic18cxx8 pic18cxx8 product identification system to order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office . * jw devices are uv erasable and can be programmed to any device configuration. jw devices meet the electrical requirement of each oscillator type. sales and support part no. x /xx xxx pattern package temperature range device device pic18cxx8 (1) , pic18cxx8t (2) ; v dd range 4.2v to 5.5v pic18lcxx5 (1) , pic18lcxx8t (2) ; v dd range 2.5v to 5.5v temperature range i = -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package cl = windowed jcerpack pt = tqfp (thin quad flatpack) l=plcc pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lc658 - i/l 301 = industrial temp., plcc package, extended v dd limits, qtp pattern #301. b) pic18lc858 - i/pt = industrial temp., tqfp package, extended v dd limits . c) pic18c658 - e/l = extended temp., plcc package, normal v dd limits . note 1: c = standard voltage range lc = wide voltage range 2: t = in tape and reel plcc, and tqfp packages only. 3: cl devices are uv erasable and can be pro- grammed to any device configuration. cl devices meet the electrical requirement of each oscillator type (including lc devices). data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. pic18cxx8 ds30475a-page 364 advanced information ? 2000 microchip technology inc. notes: ? 2000 microchip technology inc. advanced information ds30475a-page 365 pic18cxx8 notes: information contained in this publication regarding device applications and the like is intended through suggestion only and ma y be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warrant y is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patent s or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and othe r countries. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. ds30475a-page 366 advanced information ? 2000 microchip technology inc. all rights reserved. ? 2000 microchip technology incorporated. printed in the usa. 11/00 printed on recycled paper. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3838 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 dayton two prestige place, suite 130 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific china - beijing microchip technology beijing office unit 915 new china hong kong manhattan bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - shanghai microchip technology shanghai office room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 hong kong microchip asia pacific rm 2101, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o ? shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d ? activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 10/01/00 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified. |
Price & Availability of PIC18C658T-ECL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |